Renesas RA Series Quick Design Guide

Renesas RA Family RA4 Quick Design Guide
R01AN5988EU0100 Rev.1.00 Page 23 of 51
Jul.21.21
6.4 Independent Watchdog Timer Reset
This is an internal reset generated by the Independent Watchdog Timer (IWDT).
When the IWDT underflows, an independent watchdog timer reset is optionally generated (NMI can be
generated instead) and the IWDTRF bit in RSTSR1 is set to a 1. After a short delay the IWDT reset is
canceled. Refer to MCU User’s Manual for the specific timing.
6.5 Watchdog Timer Reset
This is an internal reset generated by the Watchdog Timer (WDT).
When the WDT overflows, a watchdog timer reset is optionally generated (NMI can be generated instead),
and the WDTRF bit in RSTSR1 is set to a 1. After a short delay the WDT reset is canceled. Refer to MCU
User’s Manual for the specific timing.
6.6 Voltage-Monitoring Resets
The RA4 MCU family includes circuitry that allows the MCU to protect against unsafe operation during
brownouts. On-board comparators check the supply voltage against three reference voltages, V
det0
, V
det1
,
and V
det2
. As the supply dips below each reference voltage, an interrupt or a reset can be generated. The
detection voltages V
det0
, V
det1
, and V
det2
are each selectable from 3 different levels.
When Vcc subsequently rises above V
det0
, V
det1
, or V
det2
, release from the voltage-monitoring reset proceeds
after a stabilization time has elapsed.
Low Voltage Detection is disabled after a power-on reset. Voltage monitoring can be enabled by using the
Option Function register OFS1. For more details, see the chapter “Low Voltage Detection (LVD)” in the
Hardware User’s Manual.
After an LVD Reset, the LVDnRF (n = 0, 1, 2) bit in RSTSR0 is set to 1.
6.7 Deep Software Standby Reset
Deep Software Standby Reset is an internal reset generated when deep software standby mode is canceled
by an interrupt.
When deep software standby mode is canceled, a deep software standby reset is generated, and clock
oscillation starts. On receiving the interrupt, after the Deep Standby Cancellation Wait Time (tDSBYWT 34-
35 clock cycles) has elapsed, reset is canceled, and normal processing starts. For details of the deep
software standby mode refer to the “Low Power Modes” chapter in the Hardware User’s Manual.
After a Deep Software Standby Reset, the DPSRSTF bit in RSTSR0 is set to 1.
6.8 Software Reset
The software reset is an internal reset generated by a software setting of the SYSRESETREQ bit in the
AIRCR register in the Arm core. When the SYSRESETREQ bit is set to 1, a software reset is generated.
When the internal reset time (tRESW2) elapses after the software reset is generated, the internal reset is
canceled and the CPU starts the reset exception handling. Refer to MCU User’s Manual for the specific
timing.
For details on the SYSRESETREQ bit, see the ARM
®
Cortex
®
-M33 and Cortex
®
-M4 Technical Reference
Manuals.
6.9 Other Resets
Most peripheral functions within the MCU can generate a reset under specific fault conditions. No hardware
configuration is required to enable these resets. Refer to the relevant chapters in the Hardware User’s
Manual for details of the conditions that will generate a reset for each peripheral function.
6.10 Determination of Cold/Warm Start
The RA4 MCUs allow the user to determine the cause of the reset processing. The CWSF flag in RSTSR2
indicates whether a power-on reset caused the reset processing (cold start) or a reset signal input during
operation caused the reset processing (warm start).
The flag is set to 0 when a power-on reset occurs. Otherwise, the flag is not set to 0. The flag is set to 1
when 1 is written to it through software. It is not set to 0 even on writing 0 to it.

Renesas RA Series Specifications

General

Brand	Renesas
Model	RA Series
Category	Microcontrollers
Language	English