Xilinx ChipScope Pro User Manual

26 www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1: Introduction
Table 1-10: IBERT v2.00a core for 7 Series FPGA GTP Transceivers
Feature Description
Multiple GTP Transceivers Up to fifteen transceivers can be selected per design.
Pattern Generator One pattern generator per selected GTP transceiver is used.
PRBS 7-bit, PRBS 15-bit PRBS 23-bit, PRBS 31-bit, Clk 2x, and
Clk 10x patterns are available. The desired pattern from that
set can be selected individually for each GTP transceiver at
runtime.
Pattern Checker One pattern checker per selected GTP transceiver is used. The
same pattern set is available as the pattern generator. The
pattern can be chosen for each GTP transceiver at runtime.
Fabric Width The FPGA fabric interface to the GTP transceiver can be
either 32 or 40 bits wide and selectable at generate time.
Polarity The polarity of the TX side of each GTP transceiver can be
changed at runtime.
Reset Each GTP transceiver can be reset independently. A reset is
also available to reset the entire MGT, including PLLs and
CPLLs.
Link and Lock Status Link, and CPLL/QPLL lock status are gathered for each GTP
transceiver in the core.
DRP Read The contents of the DRP space for each GTP transceiver can
be read independently of all others.
DRP Write The contents of the DRP for each GTP transceiver can be
changed at runtime, with single-bit granularity.
Ports Read The contents of the registers that monitor the GTP transceiver
ports can be read independently of others.
Ports Write The contents of the registers that control the GTP
transceiver's ports can be changed at runtime.
Status The dynamic status information for the entire core can be
read out of the core at runtime.

Xilinx ChipScope Pro Specifications

General

Brand	Xilinx
Model	ChipScope Pro
Category	Computer Hardware
Language	English