Rockwell Automation Publication 750-AT006D-EN-P - January 2022 91
Chapter 6 Active Front End Tuning
PLL Configuration
A PI controller is used to ensure proper tracking of the grid angle and frequency. The PI controller settings determine the B
W
and the
response of the system. The default setting results in a B
W
of approximately 100 Hz (628 rad/sec), which helps to ensure proper and fast
tracking, even in applications where large and fast frequency oscillations can be encountered. In applications where the grid line voltages
are highly unbalanced, the PLL unbalance feature makes reducing the B
W
of the controller unnecessary. In applications that are heavily
distorted with high harmonic content (5
th
, 7
th
, 11
th
, and so on), reducing the B
W
can be needed to alleviate the effect of these harmonics on
the accuracy of angle estimation. The relationship between the controller proportional gain K
P
, integral gain K
I
, Bandwidth B
W
, and damping
. Set the proportional and integral gains of the PI controller using 13:86 [Basic PLL Kp] and 13:87 [Basic PLL Ki].
Unbalance Rejection
As mentioned previously, the unbalance in the line voltages can degrade the performance of a standard PLL and the standard PLL must be
detuned to reject unbalance effects. The unbalance rejection is enabled by setting 13:85 [PLL Config] Bit 1 Unbl Rej. Unbalance rejection can
enhance the performance of the PLL by rejecting the effects of the unbalance in the input line voltages; no detuning is required. A key
parameter that controls the transient performance of the unbalance rejection feature is 13:89 [Unbl Rej Filt Bw]. A higher value of the B
W
results in an underdamped system, which yields faster dynamic response with an increase in the overshoot. This results in a faster
attenuation of the unbalance effect. A lower B
W
value results in an overdamped response, which results in slower attenuation of the
unbalance effect with no overshoot.
DC Offset Cancellation
This component is mainly designed to eliminate any DC offset in the measured input line voltages. The transient response to eliminate the
DC offset can be controlled using 13:90 [DC Offst Filt Bw] and 13:91 [DC Offst LPF Bw], where higher values result in a slower overdamped
response and lower values result in a faster underdamped response.
Figure 76
shows a functional block diagram that indicates the configuration parameters for the PLL. Table 33 summarizes the PLL
parameters.
B
W
K
P
2
K
P
4
4K
I
2
++
2
-------------------------------------------------
1
2
--
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