RM23712 TPS
31
12Vsb oring device. No pull-up resistors shall be on SCL or SDA inside the power supply. The
pull-up resistors should be located external to the power supply on system/application side.
3.4.2 Power Supply Management Controller (PSMC)
The PSMC device in the power supply shall derive its power of the 12Vsb output on the system side
of the oring device and shall be grounded to return. It shall be compatible with SMBus specification
2.0 and PMBusTM Power System Management Protocol Specification Part I and Part II in Revision
1.2 or later
Refer to the specification posted on www.ssiforum.org and www.pmbus.org website for details on
the power supply monitoring interface requirements and refer to followed section of supported
features. The below table reflect the power module addresses complying with the position in the
housing.
Table 34.Fan Failure Protection
PDB position and
PSMC address
3.4.2.1 Related Documents
PMBus
TM
Power System Management Protocol Specification Part I – General Requirements,
Transport And Electrical Interface; Revision 1.1 and 1.2
PMBus
TM
Power System Management Protocol Specification Part II – Command Language;
Revision 1.1 and 1.2
System Management Bus (SMBUS) Specification 2.0
3.4.2.2 Data Speed
The PSMC device in the power supply shall operate at the full 100kbps (100kHz) SMBus speed and
avoid using clock stretching that can slow down the bus. For example, the power supply is allowed
to clock stretch while parsing a command or servicing multiple interrupts or NACK.
Unsupported commands may respond with a NACK but must always set the communication error
status bit in STATUS_CML.
The PSMC may support 400kbps (400kHz) PMBus speed.
3.4.2.3 Bus Errors
The PSMC shall support SMBus clock-low timeout (T
timeout
). This capability requires the PSMC to
abort any transaction and drop off the bus if it detects the clock being held low for >25ms, and be
able to respond to new transactions within 10ms later. The total reset time from detection of the
condition till restarted, ready to receive commands condition shall not exceed 35ms.
The device must recognize SMBus START and STOP conditions on ANY clock interval. The PSMC
must not hang due to ’runt clocks’, ‘runt data’, or other out-of-spec bus timing. This is defined as
signals, logic-level glitches, setup. Or hold times that are shorter than the minimums specified by
the SMBus specifications. The PSMC is not required to operate normally, but must return to normal