Cisco XR 12000 User Manual

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|------------------|<-- SPI4 AFull 0 (0x3e80)
| |
| |
|------------------|<-- SPI4 AFull 1 (0x4b00)
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|------------------|<-- Buffer Full (0x5780)
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------------------ <-- Buffer End (0x63ff)
This table describes the significant fields shown in the display.
Table 3: show controllers plim asic ingress-channel bay Field Descriptions
DescriptionField
Identifies the primary transmit interface.Ifname
Indicates if the SPI4.2
2
channel is provisioned.SPI4.2 Channel state
Identifies the bay that hosts the specified SPI4.2
receive channel. Can be 0 or 1.
Bay number
Identifies the SPI4.2 receive channel whose
information is displayed.
Rx SPI4.2 channel number
Identifies the internal buffer associated with the
SPI4.2 receive channel.
Internal Buffer number
Embedded DRAM buffer start address in hexadecimal
format.
Rx edram buffer start address
Embedded DRAM buffer end address in hexadecimal
format.
Rx edram buffer end address
Embedded DRAM buffer size in hexadecimal format.Rx edram buffer size
Receive length buffer start address in hexadecimal
format.
Rx length buffer start address
Receive length DRAM buffer end address in
hexadecimal format.
Rx length buffer end address
Receive length DRAM buffer size in hexadecimal
format.
Rx length buffer size
Number of entries in the SPI4.2 calendar.Number of calendar entries
Average number of bytes in the interface queue.Quantum
An increment counter which indicates that the
transmit buffer is almost full. The “Buffer Almost
Full Threshold” is expressed in hexadecimal format.
Buffer Almost Full Threshold
Cisco IOS XR Advanced System Command Reference for the Cisco XR 12000 Router, Release 5.1.x
8 OL-30353-01
ASIC Driver Commands
show controllers plim asic ingress-channel bay

Cisco XR 12000 Specifications

General

Brand	Cisco
Model	XR 12000
Category	Network Router
Language	English