Texas Instruments LMK04828 User Manual

R
CLKinX
CLKinX*
Phase
Detector
PLL1
External VCXO
or Tunable
Crystal
R
N
Phase
Detector
PLL2
Dual
Internal
VCOs
External
Loop Filter
Input
Buffer
CPout1
OSCout
OSCout*
LMK0482x
CPout2
Divider
Digital Delay
Analog Delay
SDCLKoutY
SDCLKoutY*
DCLKoutX
DCLKoutX*
Partially
Integrated
Loop Filter
7 Device
Clocks
External
Loop Filter
PLL1 PLL2
7 blocks
Up to 3
inputs
N
OSCin
Internal or external loopback, user programmable
SYSREF
Analog Delay
Digital Delay
1 Global SYSREF Divider
7 SYSREF
or Device
Clocks
Up to 1 OSCout
LMK04821 , LMK04826 , LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015 www.ti.com
Figure 19. Simplified Functional Block Diagram for Nested 0-delay Dual Loop Mode
LMK04821 includes VCO1 divider on VCO1 output.
Table 7 illustrates nested 0-delay mode. This is the same as cascaded except the clock out feedback is to PLL1.
The CLKin and CLKout have the same deterministic phase relationship but the VCXO's phase will not be
deterministic to the CLKin or CLKouts.
Table 7. Nested 0-delay Dual Loop Mode Register Configuration
REGISTER
FIELD FUNCTION VALUE SELECTED VALUE
ADDRESS
PLL1_NCLK_MUX 0x13F Selects the input to the PLL1 N divider. 1 Feedback Mux
PLL2_NCLK_MUX 0x13F Selects the input to the PLL2 N divider 0 PLL2 P
FB_MUX_EN 0x13F Enables the Feedback Mux. 1 Enabled
Select between DCLKout6,
FB_MUX 0x13F Selects the output of the Feedback Mux. 0, 1, or 2
DCLKout8, SYSREF
OSCin_PD 0x140 Powers down the OSCin port. 0 Powered up
CLKin0_OUT_MUX 0x147 Selects where the output of CLKin0 is directed. 2 PLL1
CLKin1_OUT_MUX 0x147 Selects where the output of CLKin1 is directed. 0 or 2 Fin or PLL1
VCO_MUX 0x138 Selects the VCO 0, 1 or an external VCO 0 or 1 VCO 0 or VCO 1
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Texas Instruments LMK04828 Specifications

General

Brand	Texas Instruments
Model	LMK04828
Category	Motherboard
Language	English