Preface
MicroLogix 1000 Programmable Controllers User Manual
12–24
If the high-speed counter interrupt routine is executing and another high-speed
counter interrupt occurs, the second high-speed counter interrupt is saved but is
considered pending. (The PE bit is set.) The second interrupt is executed
immediately after the first one is finished executing. If a high-speed counter
interrupt occurs while a high-speed counter interrupt is pending, the most recent
high-speed counter interrupt is lost and the LS bit is set.
Using HSD
Operation
The HSD instruction disables the high-speed counter interrupt, preventing the
interrupt subroutine from being executed.
If the HSE is subsequently executed after the pending bit is set, the interrupt is
executed immediately.
This HSD instruction does not cancel an interrupt, but results in the pending bit
(C5:0/3) being set when:
• A high or low preset is reached.
• An overflow or underflow occurs.
Update High-Speed Counter Image Accumulator (OTE)
When an OUT bit instruction is addressed for the high-speed counter (C5:0) UA bit,
the value in the hardware accumulator is written to the value in the image
accumulator (C5:0.ACC). This provides you with real-time access to the hardware
accumulator value. This is in addition to the automatic transfer from the hardware
accumulator to the image accumulator that occurs each time the HSC instruction is
evaluated.
Operation
This instruction transfers the hardware accumulator to the instruction accumulator.
When the OTE/UA instruction is executed true, the hardware accumulator is loaded
to the instruction image accumulator (C5:0.ACC).
Execution Times
(µsec) when:
True False
12.00 7.00
( )
C5:0
UA
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