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Cisco XR 12000 User Manual

Cisco XR 12000
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DescriptionField
Indicates which edge of the receive SClk to use to
sample the Tstat bus. Selects rising or falling edge as
the active transmit SClk edge.
Rx SClk edge
Total number of DIP4 errors.
DIP4 is a parity algorithm where a 4-bit odd
parity is computed diagonally over status
words.
Note
DIP4 Error
SPI bus speed in MHz
7
.SPI bus speed
Committed burst size in bits for traffic transmitted on
this SPA.
Tx Burst size
Committed burst size in bits for traffic received on
this SPA.
Rx Burst size sysdb
Indicates whether receive SPI is enabled or disabled.Rx SPI state
Indicates which parameter controls the
synchronization behavior of the RXSPI module.
Rx SPI sync state
Indicates which RXSPI status protocol will be used
to transmit status.
Rx calendar mode
Maximum number of SPI receive channels supported
on this SPA.
Maximum RxSPI channels
Indicates whether transmit SPI is enabled or disabled.Tx SPI state
Indicates which parameter controls the
synchronization behavior of the TXSPI module.
Tx SPI sync state
Indicates which TXSPI status protocol will be used
to transmit status.
Tx calendar mode
Maximum number of SPI4.2 transmit channels
supported on this SPA.
Maximum Tx SPI4.2 channels
3
online insertion and removal
4
Extended Flow Control
5
security policy index
6
2-bit Diagonal Interleaved Parity
7
megahertz
Cisco IOS XR Advanced System Command Reference for the Cisco XR 12000 Router, Release 5.1.x
OL-30353-01 13
ASIC Driver Commands
show controllers plim asic spa bay

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Cisco XR 12000 Specifications

General IconGeneral
BrandCisco
ModelXR 12000
CategoryNetwork Router
LanguageEnglish

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