2-28 MAC 5500 resting ECG analysis system Revision E
2020299-020
Equipment Overview: Theory of Operation
threshold the open drain output of the comparator is used to remove the gate drive
from Q103 which will in turn switch off the com port power. The function of the
integrator is two fold. First it allows high surge currents to exist for a short time.
Secondly the integrator has a much longer recovery time due to diode CR103 which
effectively changes the integration resistor from 100K
to 1Meg. This long
recovery time results in a low duty cycle when the load is a short circuit. The low
duty cycle prevents FET Q2 from overheating when driving a short circuit.
Since the MAC 3500 contains an internal KISS pump, separate power control is
necessary for this CPU board design to support that product. An identical Switch /
Current Limiter circuit as described above for the COMM Port Power was added
exclusively for the KISS pump.
Thermal Printhead Power / Pixel Test Hardware
The FPGA provides all the interface logic for the thermal print head. A MOSFET
switch controls power. A charge pump voltage doubler driven by the FPGA
provides that switch’s gate drive.
Additional circuitry (currently unsupported) is supplied to allow the measurement of
individual dot resistance for automatic strobe width compensation and blown dot
detection. A switchable constant current source (6mA) applies a test current to the
TPH power bus. Larry then measures the TPH power bus voltage (one of the four
analog inputs he continuously monitors). By loading a single black dot into the print
head it is possible to measure its resistance. A typical TPH has an average dot
resistance of 650
. Presuming negligible driver leakage current, a single enabled
dot would drop 3.9V. While there are mitigating influences (off-pixel driver leakage
current and on-pixel driver saturation voltage) that might make accurate pixel
resistance measurements difficult, it is certainly possible to differentiate pixels of
nominal resistance from those that are blown open.
Super I/O Peripheral Controller
A PC standard Super I/O peripheral controller provides two serial channels (one
IrDA compatible, and a clock/calendar.
RS-232 Serial Ports (One Dual Mode RS-232 / IrDA)
Four serial ports are provided on two back panel Mini-DIN 8 pin connectors. The
Super I/O device provides two serial ports (COM1 and COM2) and two more
(COM3 and COM4) are provided by the ATMEL CPU. The COM2 serial port and
modem handshake lines are found in the COM2 connector. COM1, COM3, and
COM4 serial ports use pins in the COM1 connector. The COM2 serial port of the
Super I/O device also supports the IrDA interface. The COM1 serial port from Super
I/O is multiplexed with serial debug port of ATMEL. The multiplexer select pins are
controller by the jumper(W2) setting. Other than the above mentioned COM ports,
an additional com port, COM5 is provided by ATMEL. This is terminated to
daughter board interface connector and is used by the communication board
Ethernet module.
RS-232 level shifting is provided by two transceivers. Each produces the necessary
drive voltages with internal charge pumps. The devices are rated to withstand ESD
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