Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 67
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
HDMI Clock Recovery
[Figure 2-1, callout 40]
The ZCU102 board includes a Silicon Labs Si5324C jitter attenuator U70 (2 kHz - 945 MHz).
The FPGA can output the RX recovered clock to a differential I/O pair on I/O bank 66
(HDMI_REC_CLOCK_C_P, pin Y8 and HDMI_REC_CLOCK_C_N, pin Y7) for jitter attenuation.
The jitter attenuated clock (HDMI_SI5324_OUT_C_P (U108 pin 28), HDMI_SI5324_OUT_C_N
(U108 pin 29) is then routed as a reference clock to GTH Quad 128 inputs MGTREFCLK0P (U1
pin R27) and MGTREFCLK0N (U1 pin R28).
D15
HDMI_RX_CEC_SINK
LVCMOS33 24
CEC_A
TPD12S016RK
(U110)
E15
HDMI_RX_SNK_SCL
LVCMOS33 1
SCL_A
A15
HDMI_RX_SNK_SDA
LVCMOS33 1
SDA_A
A16
HDMI_TX_CEC
LVCMOS33 24
CEC_A
TPD12S016RK
(U70)
B16
HDMI_TX_HPD
LVCMOS33 3
HPD_A
H12
HDMI_SI5324_LOL
LVCMOS33 18
LOL
SI5324C (U108)
J12
HDMI_SI5324_RST
LVCMOS33 1
RST_B
F11
HDMI_SI5324_INT_ALM
LVCMOS33 3
INT_C1B
AG5
HDMI_REC_CLOCK_C_P
LVDS 16
CKIN1_P
AG4
HDMI_REC_CLOCK_C_N
LVDS 17
CKIN1_N
R27
HDMI_SI5324_OUT_C_P
(1)
28
CKOUT1_P
R28
HDMI_SI5324_OUT_C_N
(1)
29
CKOUT1_N
T33
HDMI_RX0_C_P
(1)
B7
TMDS_DATA0_P
HDMI BOTTOM
PORT(P7)
T34
HDMI_RX0_C_N
(1)
B9
TMDS_DATA0_N
P33
HDMI_RX1_C_P
(1)
B4
TMDS_DATA1_P
P34
HDMI_RX1_C_N
(1)
B6
TMDS_DATA1_N
N31
HDMI_RX2_C_P
(1)
B1
TMDS_DATA2_P
N32
HDMI_RX2_C_N
(1)
B3
TMDS_DATA2_N
N27
HDMI_RX_CLK_C_P
(1)
B10
TMDS_CLK_P
N28
HDMI_RX_CLK_C_N
(1)
B12
TMDS_CLK_N
D14
HDMI_RX_PWR_DET
LVCMOS33 3 D Q46
E14
HDMI_RX_HPD
LVCMOS33 1 G Q41
Notes:
1. U1 MGT (I/O standards do not apply).
2. SN65DP159 (U94), M24C64-W (U109), SI5324C (U108).
Table 3-29: HDMI Retimer U94 Connections to FPGA U1 (Cont’d)
XCZU9EG
(U1) Pin
Schematic Net Name I/O Standard
Connected Component
Pin No. Pin Name Device
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Xilinx ZCU102 Specifications

General

Brand	Xilinx
Model	ZCU102
Category	Motherboard
Language	English