Direct digital synthesis (DDS) generators use a phase accumulation
technique to control waveform
RAM addressing. Instead of using a
counter to generate sequential
RAM addresses, an “adder” is used.
On each clock cycle, the constant loaded into the phase increment
register (PIR) is added to the present result in the phase accumulator
(see below). The most-significant bits of the phase accumulator output
are used to address waveform
RAM — the upper 14 bits (2
14
= 16,384
RAM addresses) for the 33120A. By changing the PIR constant,
the number of clock cycles required to step through the entire waveform
RAM changes, thus changing the output frequency. When a new PIR
constant is loaded into the register, the waveform output frequency
changes phase continuously following the next clock cycle.
The 33120A uses a 48-bit phase accumulator which yields
F
clk /2
48
or approximately 142 nHz frequency resolution internally.
The phase accumulator output (the upper 14 bits) will step sequentially
through each
RAM address for smaller PIR values (lower frequencies).
However, when the
PIR is loaded with a larger value, the phase
accumulator output will skip some
RAM addresses, automatically
“sampling” the data stored in
RAM. Therefore, as the output frequency is
increased, the number of output samples per waveshape cycle will
decrease. In fact, different groups of points may be output on successive
waveform cycles.
Phase
Increment
Register
48 Bit
Phase
Register
MSB’s
(14 Bits)
48 Bit
ADDR
Time
(Clock Cycles)
48 Bit
PIR = 2
k
PIR = k
Time
(Clock Cycles)
ADDR
7
Chapter 7 Tutorial
Direct Digital Synthesis
275
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