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SLC 500 Series
Allen-Bradley SLC 500 Series User Manual
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SLC 500 Instruction
Set
Catalog Numbers 1747-L20x,
1747-L30x, 1747-L40x, 1747-L511,
1747-L514, 1747-
L524, 1747-L531,
1747-L532, 1747-
L533, 1747-L541,
1747-L542, 1747-
L543, 1747-L551,
1747-L552, 1747-L553
Reference Manual
2
Table of Contents
Notes
5
Table of Contents
5
Table of Contents
20
Default Chapter
23
Preface
23
Purpose of this Manual
23
Related Documentation
24
Who Should Use this Manual
23
Common Techniques Used in this Manual
24
Chapter 1 File Structure
25
Processor Files
25
Output and Input Data Files (Files O0: and I1:)
26
Bit Data File (B3:)
27
Status File (File S2:)
27
Timer Data File (T4:)
28
Addressing Structure
29
Counter Data File Elements (C5:)
30
Addressing Structure
31
Entering Parameters
31
Control Data File (R6:)
32
Integer Data File (N7:)
34
Float Data File (F8:)
35
Basic Instructions
37
About the Basic Instructions
38
Bit Instructions Overview
38
Chapter 2
38
Examine if Closed (XIC)
39
Examine if Open (XIO)
39
Output Energize (OTE)
40
Output Latch (OTL) and Output Unlatch (OTU)
40
Using OTL
40
Using OTU
41
One-Shot Rising (OSR)
41
Entering Parameters
41
Timer Instructions Overview
43
Entering Parameters
43
Timer On-Delay (TON)
45
Using Status Bits
45
Timer Off-Delay (TOF)
46
Using Status Bits
46
Retentive Timer (RTO)
47
Using Status Bits
48
Count up (CTU)
49
Using Status Bits
50
Counter Instructions Overview
49
How Counters Work
49
Count down (CTD)
50
Using Status Bits
51
High-Speed Counter (HSC)
51
High-Speed Counter Data Elements
52
High-Speed Counter Operation
53
Reset (RES)
56
About the Comparison Instructions
57
Chapter 3
57
Comparison Instructions
57
Comparison Instructions Overview
58
Using Indexed Word Addresses
58
Using Indirect Word Addresses
58
Equal (EQU)
58
Not Equal (NEQ)
58
Greater than (GRT)
59
Less than (LES)
59
Less than or Equal (LEQ)
59
Greater than or Equal (GEQ)
60
Masked Comparison for Equal (MEQ)
60
Entering Parameters
60
Limit Test (LIM)
61
Entering Parameters
61
Math Instructions
63
About the Math Instructions
64
Chapter 4
64
Math Instructions Overview
64
Entering Parameters
64
Using Indexed Word Addresses
64
Using Indirect Word Addresses
64
Updates to Arithmetic Status Bits
65
Overflow Trap Bit, S:5/0
65
Updates to the Math Register, S:13 and S:14
65
Using Floating Point Data File (F8:)
66
Add (ADD)
67
Updates to Arithmetic Status Bits
67
Subtract (SUB)
67
32-Bit Addition and Subtraction
68
Math Overflow Selection Bit S:2/14
68
Multiply (MUL)
70
Updates to Arithmetic Status Bits
70
Updates to the Math Register, S:13 and S:14
71
Divide (DIV)
71
Updates to Arithmetic Status Bits
71
Updates to the Math Registers, S:13 and S:14
72
Double Divide (DDV)
73
Updates to Arithmetic Status Bits
73
Updates to the Math Registers, S:13 and S:14
73
Clear (CLR)
74
Updates to Arithmetic Status Bits
74
Square Root (SQR)
74
Scale with Parameters (SCP)
75
Entering Parameters
75
Updates to Arithmetic Status Bits
76
Application Examples
76
Scale Data (SCL)
77
Entering Parameters
78
Updates to Arithmetic Status Bits
78
Application Example 1 - Converting 4 to 20 Ma Analog Input Signal to PID Process Variable
79
Application Example 2 - Scaling an Analog Input to Control an Analog Output
80
Ramp Instruction (RMP)
82
Instruction Operation
84
RMP Equation
85
Continuous Operation
85
Absolute (ABS)
86
Entering Parameters
86
Updates to Arithmetic Status Bits
86
Compute (CPT)
87
Entering Parameters
87
Updates to Arithmetic Status Bits
88
Application Example
88
Swap (SWP)
90
Entering Parameters
90
Arc Cosine (ACS)
91
Arc Sine (ASN)
91
Updates to Arithmetic Status Bits
91
Arc Tangent (ATN)
92
Updates to Arithmetic Status Bits
92
Cosine (COS)
92
Log to the Base 10 (LOG)
93
Natural Log (LN)
93
Updates to Arithmetic Status Bits
93
Sine (SIN)
94
Updates to Arithmetic Status Bits
94
Tangent (TAN)
94
To the Power of y (XPY)
95
Updates to Arithmetic Status Bits
95
Data Handling Instructions
97
Chapter 5 Convert to BCD (TOD)
98
Updates to Arithmetic Status Bits
98
Updates to the Math Register, S:13 and S:14
99
Convert from BCD (FRD)
101
Updates to Arithmetic Status Bits
101
Changes to the Math Register, S:13 and S:14
102
Radian to Degrees (DEG)
104
Entering Parameters
104
Updates to Arithmetic Status Bits
105
Degrees to Radians (RAD)
105
Entering Parameters
105
Updates to Arithmetic Status Bits
106
Decode 4 to 1 of 16 (DCD)
106
Entering Parameters
107
Encode 1 of 16 to 4 (ENC)
107
Entering Parameters
108
Updates to Arithmetic Status Bits
108
Copy File (COP) and Fill File (FLL) Instructions
109
Using COP
109
Using FLL
110
Move and Logical Instructions Overview
112
Entering Parameters
112
Using Indexed Word Addresses
112
Updates to Arithmetic Status Bits
112
Using Indirect Word Addresses
112
Updates to the Math Register, S:13 and S:14
113
Entering Mask Values
113
Move (MOV)
113
Entering Parameters
113
Updates to Arithmetic Status Bits
113
Masked Move (MVM)
114
Entering Parameters
114
Updates to Arithmetic Status Bits
114
And (AND)
116
Updates to Arithmetic Status Bits
116
Or (OR)
117
Updates to Arithmetic Status Bits
117
Exclusive or (XOR)
118
Updates to Arithmetic Status Bits
118
Not (NOT)
119
Updates to Arithmetic Status Bits
119
Negate (NEG)
120
Updates to Arithmetic Status Bits
120
FIFO and LIFO Instructions Overview
121
Entering Parameters
121
Effects on Index Register S:24
122
FIFO Load (FFL) and FIFO Unload (FFU)
122
FFL Instruction Operation
123
FFU Instruction Operation
123
LIFO Load (LFL) and LIFO Unload (LFU)
124
LFL Instruction Operation
125
LFU Instruction Operation
125
About the Program Flow Control Instructions
127
Chapter 6
127
Program Flow Instructions
127
Jump to Label (JMP) and Label (LBL)
128
Entering Parameters
128
Using JMP
128
Using LBL
129
Jump to Subroutine (JSR), Subroutine (SBR), and Return (RET)
129
Nesting Subroutine Files
130
Using JSR
130
Using SBR
131
Using RET
131
Master Control Reset (MCR)
132
Processor Operation
132
Temporary End (TND)
133
Immediate Input with Mask (IIM)
134
Entering Parameters
135
Suspend (SUS)
134
Entering Parameters
134
Immediate Output with Mask (IOM)
135
I/O Refresh (REF)
136
Using an SLC 5/02 Processor
136
Using SLC 5/03 and Higher Processors
136
About the Application Specific Instructions
138
Application Specific Instructions
138
Bit Shift Instructions Overview
138
Entering Parameters
138
Effects on Index Register S:24
140
Chapter 7
138
Bit Shift Left (BSL)
140
Bit Shift Right (BSR)
141
Use BSR
141
Sequencer Instructions Overview
141
Effects on Index Register S:24
141
Applications Requiring more than 16 Bits
142
Sequencer Output (SQO) Sequencer Compare (SQC)
142
Enter Parameters
142
Use SQO
144
Use SQC
146
Sequencer Load (SQL)
148
Enter Parameters
148
Operation
150
Read High-Speed Clock and Compute Time Difference Overview
151
RHC Instruction Operation
151
TDF Instruction Operation
152
Compute Time Difference Instruction (TDF)
153
Read High-Speed Clock Instruction (RHC)
153
Enter Parameters
153
File Bit Comparison (FBC) and Diagnostic Detect (DDT)
154
Select the Search Mode
154
Enter Parameters
156
Use Status Bits
157
Read Program Checksum (RPC)
159
Enter Parameters
159
Block Transfer Instructions
162
Chapter 8
162
RIO Block Transfer General Functional Overview
162
Entering Parameters for BTR and BTW
162
Control Status Bits
163
Instruction Operation
167
Programming Examples
168
Comparison to the PLC-5 BTR and BTW
171
Chapter 9
173
Overview
173
Proportional Integral Derivative Instruction
173
The PID Concept
173
The PID Equation
174
The PID Instruction
175
Entering Parameters
175
PID Control Block Layout
177
Controller Gain (Kc)
178
Reset Term (Ti)
178
Rate Term (Td)
179
Feed Forward/Bias
179
Mode (TM)
179
Loop Update
180
Deadband
180
Scaled Error
181
Auto / Manual (AM)
181
Control (CM)
182
Deadband (DB)
182
Reset and Gain Enhancement Bit (RG)
182
Setpoint Scaling (SC)
183
Loop Update Time too Fast (TF)
183
Derivative Rate Action Bit (DA)
184
Output Alarm Upper Limit (UL)
184
Output Alarm Lower Limit (LL)
184
Setpoint out of Range (SP)
185
PV out of Range (PV)
185
PID Done (DN)
185
PID Rational Approximation Bit (RA)
186
PID Enable (EN)
186
Integral Sum
186
Input Parameters
187
Setpoint (SP)
187
Scaled Process Variable (SPV)
188
Setpoint Maximum Scaled (SMAX)
188
Setpoint Minimum Scaled (SMIN)
189
Output Parameters
190
Control Variable (CV)
190
Control Variable Percent (CV%)
191
Output Limiting Enable (OL)
191
Output Maximum (CVH)
192
Output Minimum (CVL)
192
Runtime Errors
193
PID and Analog I/O Scaling
195
Using the SCL Instruction
196
Using the SCP Instruction
196
Application Notes
199
Input/Output Ranges
199
Scaling to Engineering Units
199
Output Alarms
200
Output Limiting with Anti-Reset Windup
201
The Manual Mode
201
PID Rungstate
202
Time Proportioning Outputs
202
ASCII Instruction Overview
206
ASCII Instructions
206
Chapter 10
206
Protocol Parameter Overview
206
Entering Parameters
209
Test ASCII Buffer for Line (ABL)
210
Entering Parameters
210
Number of ASCII Characters in Buffer (ACB)
211
Entering Parameters
211
String to Integer (ACI)
212
ASCII Clear Receive And/Or Transmit Buffer (ACL)
213
Entering Parameters
214
String Concatenate (ACN)
215
Entering Parameters
215
String Extract (AEX)
216
Entering Parameters
216
ASCII Handshake Lines (AHL)
217
Entering Parameters
217
Integer to String (AIC)
218
ASCII Read Characters (ARD)
219
Entering Parameters
219
Timing Diagram for a Successful ARD, ARL, AWA, and AWT Instructions
220
ASCII Read Line (ARL)
221
Entering Parameters
221
String Search (ASC)
222
Entering Parameters
222
ASCII String Compare (ASR)
223
Entering Parameters
223
ASCII Write with Append (AWA)
224
Entering Parameters
224
Using Inline Indirection
225
ASCII Write (AWT)
226
Entering Parameters
226
ASCII Instruction Error Codes
228
ASCII Conversion Table
229
Chapter 11 User Fault Routine Overview
234
Status File Data Saved
235
Creating a User Fault Subroutine
235
User Interrupt Routine Application Example
236
Understanding Interrupt Routines
234
Selectable Timed Interrupt Overview
240
Basic Programming Procedure for the STI Function
240
Operation
241
STI Subroutine Content
241
Interrupt Latency and Interrupt Occurrences
241
Interrupt Priorities
243
Status File Data Saved
243
STI Parameters
244
STD and STE Instructions
248
Selectable Timed Disable - STD
248
Selectable Timed Enable - STE
248
STD/STE Zone Example
248
Selectable Timed Start (STS)
249
Discrete Input Interrupt Overview
250
Basic Programming Procedure for the DII Function
250
Operation
251
Counter Mode
251
Event Mode
252
DII Subroutine Content
252
Interrupt Latency and Interrupt Occurrences
253
Interrupt Priorities
254
Status File Data Saved
254
Reconfigurability
254
DII Parameters
255
Discrete Input Interrupt Application Example
257
I/O Interrupt Overview (ISR)
259
Function
259
Operation
259
Interrupt Subroutine (ISR) Content
260
Interrupt Latency and Interrupt Occurrences
260
Interrupt Priorities
261
Status File Data Saved
262
I/O Interrupt Parameters
262
I/O Interrupt Disable (IID) and I/O Interrupt Enable (IIE)
264
IID Operation
264
IIE Operation
265
IID/IIE Zone Example
265
Interrupt Subroutine (INT)
266
Reset Pending Interrupt (RPI)
266
Entering Parameters
266
SLC Communication Instructions
267
About the Communication Instructions
268
Chapter 12
268
Service Communications (SVC)
269
Use an SLC 5/02 Processor
269
Use SLC 5/03 and Higher Processors
269
Channel Servicing
270
Message Instruction Overview
271
MSG Instruction Operation
271
MSG Instruction Configuration Options
277
MSG Instruction Parameters
277
MSG Instruction Setup Screen Parameters
279
MSG Instruction Setup Screen Status Bits
293
MSG Instruction Control Block
296
Status Bit Sequencing for SLC 5/03, SLC 5/04, and SLC 5/05 MSG Instruction
303
Rung Goes True
303
Next End of Scan
305
Successful Receipt of Packet
305
An ACK Is Not Received
306
Target Node Sends a Reply Packet
306
MSG Instruction Error Codes
307
Explicit Message Instruction Overview
310
Controlnet Explicit Message (CEM)
311
CEM Instruction Parameters
311
CEM Instruction Setup Screen Parameters
312
Devicenet Explicit Message (DEM)
318
DEM Instruction Parameters
318
DEM Instruction Setup Screen Parameters
318
Ethernet/Ip Explicit Message (EEM)
324
EEM Instruction Parameters
324
EEM Instruction Setup Screen Parameters
324
Communication Driver Overview
332
Chapter 13 DH-485 Communications
334
DH-485 Network Protocol
334
DH-485 Network Considerations
335
Data Highway Plus Communications
340
Configuring Channel 1 for DH
342
DH+ Channel Status
343
Global Status Word Overview
348
Ethernet Communications
352
SLC 5/05 Performance Considerations
352
SLC 5/05 and PC Connections to the Ethernet Network
353
Configuring Channel 1 for Ethernet
354
Ethernet Channel Status
358
Configuration Via BOOTP
361
Using the Rockwell BOOTP Utility
363
SLC 5/05 Embedded Web Server Capability
365
Module Information
365
TCP/IP Configuration
366
Diagnostic Information
367
Data Table Memory Map
368
Data Table Monitor
370
User Provided Pages
371
DF1 Full-Duplex Communications
379
Configuring Channel 0 for DF1 Full-Duplex
379
DF1 Full-Duplex Channel Status
383
DF1 Half-Duplex Communications
385
DF1 Half-Duplex Master Broadcast
385
DF1 Half-Duplex Slave Broadcast
385
Configuring Channel 0 for Standard Polling Mode DF1 Half-Duplex Master
386
Minimum DF1 Half-Duplex Master Channel 0 ACK Timeout
391
Determining Minimum Master ACK Timeout
392
Monitor Active Stations
393
Configuring Channel 0 for Message-Based Polling Mode DF1
393
Half-Duplex Master
393
DF1 Half-Duplex Master Channel Status
398
Configuring Channel 0 for DF1 Half-Duplex Slave
399
Configuring Channel 0 Poll Timeout
403
DF1 Half-Duplex Slave Channel Status
404
DF1 Radio Modem Communications
406
DF1 Radio Modem System Limitations
407
Configuring Channel 0 for DF1 Radio Modem
408
DF1 Radio Modem Channel Status
411
Configuring the Store & Forward Table
412
Using Modems that Support DF1 Communication Protocols
414
Dial-Up Phone Modems
414
Leased-Line Modems
414
Radio Modems
415
Line Drivers
415
Modem Control Line Operation in SLC 5/03, SLC 5/04 and
416
DF1 Full-Duplex
416
DF1 Half-Duplex Slave
416
DF1 Half-Duplex Master
417
DF1 Radio Modem
418
Modbus RTU Master
418
RTS Send Delay and RTS off Delay Parameters
419
Modbus RTU Protocol
420
Modbus RTU Master
420
Configuring a Channel for Modbus RTU Master
421
Modbus RTU Master Channel Status
424
Modbus Commands
426
Modbus Error Codes
427
ASCII Communications
428
Configuring Channel 0 for ASCII Communications
428
Chapter 14
431
Remote I/O Passthru
431
SLC Passthru Communications
431
Channel-To-Channel Passthru
432
Additional SLC 5/03 Passthru Status Bits
434
Using Rslinx Classic, Version 2.50 and Higher, with SLC 5/03
435
Passthru
435
SLC 5/03 Passthru Error Codes
437
Using Rslinx Classic, Version 2.50 and Higher, with SLC 5/04
438
Passthru
438
Creating and Filling out the Passthru Routing Table File
439
Using Rslinx Classic, Version 2.50 and Higher, with SLC 5/05
441
Passthru
441
SLC 5/05 Passthru Error Codes
443
Optimizing Rslinx Channel 1 to DF1 Half-Duplex Master/Df1
443
Radio Modem Passthru
443
Devicenet Passthru
432
Chapter 15 Local Versus Remote Type Message
447
Local Message
447
Remote Message
447
Messaging Examples
447
Remote Terminology
448
Remote Bridge Address
448
Remote Station Address
448
Remote Bridge Link ID
448
SLC 5/03 Passthru Examples
449
Passthru Example: DF1 to DH-485
449
Passthru Example: DH-485 to DF1
452
SLC 5/04 Passthru Examples
458
Passthru Example: DF1 to DH
458
Passthru Example: DH+ to DF1
461
Passthru Example: DH-485 to DH
462
SLC 5/05 Passthru Examples
464
Passthru Example: DF1 to Ethernet
464
SLC 5/05 (IP Address 100.100.115.9) Bridge
466
Passthru Routing Table
467
Passthru Example: Ethernet to DF1
468
Passthru Example: DH-485 to Ethernet
469
Passthru Example: Ethernet to DH-485
470
Remote Examples
471
Remote Example: Network Overview
471
Network Message Example: SLC 5/04 to SLC 5/02 Via DHRIO and KA5
472
Network Message Example: SLC 5/04 to SLC 5/03 Via DHRIO and KA5
473
Network Message Example: SLC 5/04 to SLC
475
Network Message Example: SLC 5/04 to SLC
476
Network Message Example: SLC 5/04 to SLC 5/05 Via DHRIO and ENET
477
Network Message Example: SLC 5/05 to SLC 5/04 Via ENET and DHRIO
478
Network Message Example: SLC 5/05 to SLC 5/03 Via ENET, CNB and KFC
479
Network Message Example: SLC 5/05 to SLC 5/03 Via ENET, DHRIO and KA5
480
Chapter 16 Automatically Clear Faults
483
SLC Processors
483
Troubleshooting Faults
483
Manually Clear Faults
484
Use the Fault Routine
484
SLC Processor Faults
485
Powerup Errors
485
Going-To-Run Errors
486
Run Errors
488
User Program Instruction Errors
491
I/O Errors
493
Troubleshoot SLC 5/03 and Higher Processors
497
Powerup LED Display
497
Identify Processor Errors While Downloading an Operating System
497
Appendix A
499
Original Release
499
Enhancements
499
OS300, Series A, FRN 1
499
Released: March 1994
499
Released: August 1994
500
Enhancements
500
OS302, Series C, FRN
504
OS401, Series C, FRN
504
OS501, Series C, FRN
504
Enhancements
504
OS302, Series C, FRN 3
505
OS401, Series C, FRN 3
505
OS501, Series C, FRN 3
505
Enhancements
505
OS302, Series C, FRN 4
509
OS401, Series C, FRN 4
509
OS501, Series C, FRN 4
509
Enhancements
509
Appendix B
521
Status File Overview
521
Status File Details
524
Conventions Used in the Displays
524
Other manuals for Allen-Bradley SLC 500 Series
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Allen-Bradley SLC 500 Series Specifications
General
Brand
Allen-Bradley
Model
SLC 500 Series
Category
Controller
Language
English
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