Publication 1747-RM001G-EN-P - November 2008
Math Instructions 4-9
Updates to the Math Register, S:13 and S:14
During integer operation, S:13 and S:14 contain the 32-bit signed result of the
multiply instruction. This result is valid at overflow.
Divide (DIV)
Use the DIV instruction to divide one value (source A) by another (source B).
The rounded quotient is then placed in the destination. If the remainder is 0.5
or greater, round up occurs in the destination. The unrounded quotient is
stored in the most significant word of the math register. The remainder is
placed in the least significant word of the math register.
Updates to Arithmetic Status Bits
The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file.
After an instruction is executed, the arithmetic status bits in the status file are
updated.
Table 4.7 Processor Function
With this Bit The Processor
S:0/0 Carry (C) always resets.
S:0/1 Overflow (V) sets if overflow is detected at destination; otherwise resets. On
overflow, the minor error flag is also set. The value -32,768 or
32,767 is placed in the destination. Exception: If you are using
an SLC 5/02 or higher processor and have S:2/14 (math overflow
selection bit) set, then the unsigned, truncated least significant
16-bits of the result remains in the destination. For floating
point destinations, the overflow result remains in the
destination.
S:0/2 Zero (Z) sets if result is zero; otherwise resets.
S:0/3 Sign (S) sets if result is negative; otherwise resets.
TIP
For floating point operation, the math register does
not change.
DIV
Divide
Source A N7:23
0<
Source B N7:24
0<
Dest N7:25
0<
DIV
Output Instruction
Fixed SLC
5/01
SLC
5/02
SLC
5/03
SLC
5/04
SLC
5/05
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