Publication 1747-RM001G-EN-P - November 2008
11-16 Understanding Interrupt Routines
STD and STE Instructions
The STD and STE instructions are used to create zones in which STI ladder
execution cannot occur. The STI timer continues to operate at the rate present
in word S:30.
Selectable Timed Disable - STD
When true, this instruction resets the STI enable bit and prevents the STI
subroutine from executing. When the rung goes false, the STI enable bit
remains reset until a true STS or STE instruction is executed. The STI timer
continues to operate while the enable bit is reset.
Selectable Timed Enable - STE
This instruction, upon a false-true transition of the rung, sets the STI enable
bit and allows execution of the STI subroutine. When the rung goes false, the
STI enable bit remains set until a true STD instruction is executed. This
instruction has no effect on the operation of the STI timer or setpoint. When
the enable bit is set, the first execution of the STI subroutine can occur at any
fraction of the timing cycle up to a full timing cycle later.
STD/STE Zone Example
In the program that follows, the STI function is in effect. The STD and STE
instructions in rungs 6 and 12 are included in the ladder program to avoid
having STI subroutine execution at any point in rungs 7 through 11.
The STD instruction (rung 6) resets the STI enable bit and the STE instruction
(rung 12) sets the enable bit again. The STI timer increments and may time out
in the STD zone, setting the pending bit S:2/0 and overrun bit S:5/10.
The first pass bit S:1/15 and the STE instruction in rung 0 are included to
insure that the STI function is initialized following a power cycle. You should
include this rung any time your program contains an STD/STE zone or an
STD instruction.
Fixed SLC
5/01
SLC
5/02
SLC
5/03
SLC
5/04
SLC
5/05
••••
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