Publication 1747-RM001G-EN-P - November 2008
Basic Instructions 2-5
When enabled, the latch instruction tells the controller to turn on the
addressed bit. Thereafter, the bit remains on, regardless of the rung condition,
until the bit is turned off (typically by a OTU instruction in another rung).
Using OTU
When you assign an address to the OTU instruction that corresponds to the
address of a physical output, the output device wired to this screw terminal is
de-energized when the bit is cleared (turned off or disabled).
The unlatch instruction tells the controller to turn off the addressed bit.
Thereafter, the bit remains off, regardless of the rung condition, until it is
turned on (typically by a OTL instruction in another rung).
One-shot Rising (OSR)
The OSR instruction is a retentive input instruction that triggers an event to
occur one time. Use the OSR instruction when an event must start based on
the change of state of the rung from false-to-true.
When the rung conditions preceding the OSR instruction go from
false-to-true, the OSR instruction will be true for one scan. After one scan is
complete, the OSR instruction becomes false, even if the rung conditions
preceding it remain true. The OSR instruction will only become true again if
the rung conditions preceding it transition from false-to-true.
The SLC 500 and SLC 5/01 processors allow you to use one OSR instruction
per output in a rung; the OSR cannot be within a branch. The SLC 5/02 and
higher processors allow you to use one OSR instruction per output in a rung;
putting the OSR within a branch is permitted.
Entering Parameters
The address assigned to the OSR instruction is not the one-shot address
referenced by your program, nor does it indicate the state of the OSR
instruction. This address allows the OSR instruction to remember its previous
rung state.
Use a bit address from either the bit or integer data file. The addressed bit is
set (1) for one scan when rung conditions preceding the OSR instruction are
true (even if the OSR instruction becomes false); the bit is reset (0) when rung
conditions preceding the OSR instruction are false.
[OSR]
Input Instruction
Fixed SLC
5/01
SLC
5/02
SLC
5/03
SLC
5/04
SLC
5/05
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