Publication 1747-RM001G-EN-P - November 2008
2-6 Basic Instructions
Do not use an input or output address to program the address parameter of
the OSR instruction.
Examples
The following rungs illustrate the use of the OSR instruction. The first four
rungs apply to SLC 500 and SLC 5/01 processors. The fifth rung involves
output branching and applies to the SLC 5/02 and higher processors.
TIP
The bit address you use for this instruction must be
unique. Do not use it elsewhere in the program.
] [
I:1.0
0
[OSR]
B3
0
( )
O:3.0
0
TO BCD
Source Tf:0.ACC
Dest O:3
] [
I:1.0
0
[OSR]
B3
0
TOD
SLC 500 and SLC 5/01 Processors
When the input instruction goes from false-to-true, the OSR instruction
conditions the rung so that the output goes true for one program scan. The
output goes false and remains false for successive scans until the input makes
another false-to-true transition.
In this case, the accumulated value of a timer is converted to BCD and moved to an
output word where an LED display is connected. When the timer is running, the
accumulated value is changing rapidly. This value can be frozen and displayed for
each false-to-true transition of the input condition of the rung.
] [
I:1.0
0
[OSR]
B3
0
O:3.0
0
O:3.0
1
( )
( )
] [
I:1.0
0
[OSR]
B3
0
O:3.0
0
O:3.0
1
( )
( )
Using an OSR Instruction in a Branch (SLC 500 and SLC 5/01 Processors)
In the above rung, the OSR instruction is not permitted inside a branch.
In this case, the OSR instruction is not in the branch so the rung is legal.
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