Publication 1747-RM001G-EN-P - November 2008
Math Instructions 4-11
Double Divide (DDV)
The 32-bit content of the math register is divided by the 16-bit source value
and the rounded quotient is placed in the destination. If the remainder is 0.5 or
greater, the destination is rounded up.
Updates to Arithmetic Status Bits
The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file.
After an instruction is executed, the arithmetic status bits in the status file are
updated.
Updates to the Math Registers, S:13 and S:14
Initially contains the dividend of the DDV operation. Upon instruction
execution, the unrounded quotient is placed in the most significant word of
the math register. The remainder is placed in the least significant word of the
math register.
DDV
Double Divide
Source N7:26
0<
Dest N7:27
0<
DDV
Output Instruction
ixed SLC
5/01
SLC
5/02
SLC
5/03
SLC
5/04
SLC
5/05
• •••••
TIP
This instruction typically follows a MUL instruction
that creates a 32-bit result.
Table 4.9 Processor Function
With this Bit The Processor
S:0/0 Carry (C) always resets.
S:0/1 Overflow (V) sets if division by zero or if result is greater than 32,767 or
less than -32,768; otherwise resets. On overflow, the minor
error flag is also set. The value 32,767 is placed in the
destination.
S:0/2 Zero (Z) sets if result is zero; otherwise resets.
S:0/3 Sign (S) sets if result is negative; otherwise resets; undefined if
overflow is set.
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