PC Specialist's Handbook ErgoPro e-, x- and s- Series
First Edition, Release 4 - June 1998 Page 57
BIOS check points
This table shows the checkpoint number (hex) and what BIOS is doing while this checkpoint is displayed :
If the code is not shown on this list, contact ICL Service Provider.
01 Disable internal cache
02 Disable parity checking. Do early chipset init. Disable DMA-controllers, CMOS and RTC.
03 Initialize the 8254 timer, all channels.
04 Set up DMA controllers (see chp 1C-22 below)
06 Chipset unique code (e.g. DRAM configuration).
08 CMOS battery fail detected, CMOS is set to default, XCMOS (PCMOS) is cleared.
09 Initialize interrupt controllers.
0A Check system memory, 64K-256K
10 Reset cause = Normal power on. Check CPU general purpose registers, halt if failure.
11 Disable parity checking. Port 61 = FC
12 Disable both DMA controllers. Port 08 = 04, Port D0 = 04
13 Disable RTC interrupts by clearing bits 7 - 3 of CMOS cell 0B and then reading cell 0C.
14 Turn off color video signal. Port 3D8 = 01
15 Turn off monochrome video signal. Port 3B8 = 01
16 Turn off EGA video signal and selecting color palette zero. Port 3C0 = 0
19 Initialize the 8254 timer, all channels. Port 43 = 36, Port 40 = 00, 00
1C Reset both DMA controllers. Port 0D = Anything, Port DA = Anything
1D Initialize DMA channel 0, both controllers. Port 0B = 40, Port D6 = C0
1E Initialize DMA channel 1, both controllers. Port 0B = 41, Port D6 = 41
1F Initialize DMA channel 2, both controllers. Port 0B = 42, Port D6 = 42
20 Initialize DMA channel 3, both controllers. Port 0B = 43, Port D6 = 43
21 Clear DMA page registers 80 to 8F.
22 Enable both DMA controllers and clear mask of master controller. Port D0 = 00, Port 08 = 00, Port
D4 = 00
23 Test refresh by waiting for a 'HIGH' on bit 04 of port 61.
24 Test refresh by waiting for a 'LOW' on bit 04 of port 61. Wait for 10000 refresh cycles to DRAM.
25 Test first 64k memory address lines by writing 11 at 0000:8000, 10 at 0000:4000 and so on until
writing 01 at 0000:0000. These locations are then verified.
For boot block code only:
Copy boot PROM to RAM and jump into RAM. Set up interrupt vectors 00-1F. Copy constants to RAM. Test
CMOS battery fail bit (if fail, see chp 08).
26 Test first 64k memory address lines by writing 11 at 0000:8000, 10 at 0000:4000 and so on until
writing 01 at 0000:0000. These locations are then verified.
27 Enable parity checking. Port 61 = F0
28 Fill lower 64k of RAM with FFFF.
29 Compare lower 64k of RAM against FFFF.
2A Check for any parity error.
2B Fill lower 64k of RAM with 0000.
2C Compare lower 64k of RAM against 0000.
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