Remote Control
Copyright © ITECH Electronic Co., Ltd. 13
Circulation power
Sending the *CLS command
Note: The MAV bit may or may not be cleared.
Service request enable register
This register is programmed by you and serves as a mask for the status
summary message bits (B2, B3, B4, B5, and B7) of the status byte
register.When masked, a set summary bit in the status byte register cannot set
bit B6 (MSS/RQS) of the status byte register. Conversely, when unmasked, a
set summary bit in the status byte register sets bit B6.
A status summary message bit in the status byte register is masked when the
corresponding bit in the service request enable register is cleared.When the
masked summary bit in the status byte register sets, it is ANDed with the
corresponding cleared bit in the service request enable register.The logic “1”
output of the AND gate is applied to the input of the OR gate and, thus, sets the
MSS/RQS bit in he status byte register.
The individual bits of the service request enable register can be set or cleared
by using the following common command:
*SRE <NRf>*SRE <NRf>
To read the service request enable register, use the *SRE? query command.
The service request enable register clears when power is cycled or a parameter
(n) value of zero is sent with the *SRE command *SRE 0).
1.12 Serial poll and SRQ
Any enabled event summary bit that goes from 0 to 1 will set RQS and generate
a service request (SRQ). In your test program, you can periodically read the
status byte register to check if a service request (SRQ) has occurred and what
caused it. If an SRQ occurs, the program can, for example, branch to an
appropriate subroutine that will service the request. Typically, service requests
(SRQs) are managed by the serial poll sequence of the electronic load. If an
SRQ does not occur, bit B6 (RQS) of the status byte register will remain cleared
and the program will simply proceed normally after the serial poll is performed.
If an SRQ does occur, bit B6 of the status byte register will set and the program
can branch to a service subroutine when the SRQ is detected by the serial poll.
The serial poll automatically resets RQS of the status byte register. This allows
subsequent serial polls to monitor bit B6 for an SRQ occurrence generated by
other event types. After a serial poll, the same event can cause another SRQ,
even if the event register that caused the first SRQ has not been cleared.
A serial poll clears RQS but does not clear MSS. The MSS bit stays set until all
status byte event summary bits are cleared.
1.13 Trigger Model (GPIB Operation)
This section describes how the electronic load operates over the GPIB bus. It is
called the trigger model because operation is controlled by SCPI commands
from the Trigger subsystem. Key SCPI commands are included in the trigger
model.
Trigger Model Operation
Once the instrument is taken out of idle state, operation proceeds through the
trigger model down to the device action.
A control source is used to hold up operation until the programmed event
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