IEEE-488 Reference
3-15
3.8.3 Event registers
As shown in the illustrations, each status register set has an
event register. An event register is a latched, read-only regis-
ter whose bits are set by the corresponding condition register
and transition filter. Once a bit in an event register is set, it
remains set (latched) until the register is cleared by a specific
clearing operation. The bits of an event register are logically
ANDed with the bits of the corresponding enable register
and applied to an OR gate. The output of the OR gate is ap-
plied to another register set or to the Status Byte Register.
The *ESR? Common Command is used to read the Standard
Event Register (see paragraph 3.11.3). All other event regis-
ters are read using the [:EVENT]? query commands in the
STATus Subsystem (see paragraph 3.20).
An event register is cleared when it is read. The following
operations clear all event registers:
• Cycling power
• Sending *CLS
3.8.4 Enable registers
As shown in the illustrations, each status register set has an
enable register. An enable register is programmed by the user
and serves as a mask for the corresponding event register. An
event bit is masked when the corresponding bit in the enable
register is cleared (0). When masked, a set bit in an event reg-
ister cannot set a bit in a following register set or in the Status
Byte Register (1 AND 0 = 0).
To use the Status Byte Register to detect events (i.e. serial
poll), you must unmask the events by setting (1) the appro-
priate bits of the enable registers.
The Standard Event Status Enable Register is programmed
and queried using the *ESE and *ESE? Common Com-
mands respectively (see paragraph 3.11.2). All other enable
registers are programmed and queried using the :ENABle
and :ENABle? commands in the STATus Subsystem (see
paragraph 3.20).
An enable register is not cleared when it is read. The Enable
registers are affected by the following operations:
• Cycling power — Clears all enable registers
• :STATus:PRESet clears the following enable registers:
Operation Event Enable Register
Questionable Event Enable Register
Measurement Event Enable Register
• :STATus:PRESet sets all bits of the following enable
registers:
Trigger Event Enable Register
Arm Event Enable Register
Sequence Event Enable Register
• *ESE 0 — Clears the Standard Event Status Enable
Register.
3.8.5 Queues
The Model 6517A uses two queues; the Output Queue and
the Error Queue. The queues are first-in first-out (FIFO) reg-
isters. The Output Queue is used to hold readings and re-
sponse messages, and the Error Queue is used to hold error
messages and status messages. The Model 6517A status
model (Figure 3-5) shows how the two queues are structured
with the other registers.
Output Queue — The Output Queue is used to hold data that
pertains to the normal operation of the instrument. For exam-
ple, when a query command is sent, the response message is
placed in the Output Queue.
When data is placed in the Output Queue, the Message
Available (MAV) bit in the Status Byte Register sets. A data
message is cleared from the Output Queue when it is read.
The Output Queue is considered cleared when it is empty. An
empty Output Queue clears the MAV bit in the Status Byte
Register.
A message from the Output Queue is read by addressing the
Model 6517A to talk after the appropriate query is sent.
Error Queue — The Error Queue is used to hold error mes-
sages and status messages. When an error or status event oc-
curs, a message that defines the error/status is placed in the
Error Queue. This queue will hold up to 10 messages.
When a message is placed in the Error Queue, the Error
Available (EAV) bit in the Status Byte Register is set. An er-
ror message is cleared from the Error/Status Queue when it
is read. The Error Queue is considered cleared when it is
empty. An empty Error Queue clears the EAV bit in the Sta-
tus Byte Register. An error message from the Error Queue is
read by sending either of the following SCPI query com-
mands and then addressing the Model 6517A to talk:
:SYSTem:ERRor?
:STATus:QUEue?
Refer to paragraphs 3.20.7 (:STATus:QUEue?) and 3.21.5
(:SYSTem:ERRor?) for complete information on reading er-
ror messages.
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