Processing States
MOTOROLA
MC68030 USER’S MANUAL
4-3
When the M bit is clear, the MC68030 is in the interrupt mode of the supervisor privilege
level, and operation is the same as in the MC68000, MC68008, and MC68010 supervisor
mode. (The processor is in this mode after a reset operation.) All supervisor stack pointer
references access the interrupt stack pointer (ISP) in this mode.
The value of the M bit in the status register does not affect execution of privileged
instructions; both master and interrupt modes are at the supervisor privilege level.
Instructions that affect the M bit are MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, and
RTE. Also, the processor automatically saves the M-bit value and clears it in the SR as part
of the exception processing for interrupts.
All exception processing is performed at the supervisor privilege level. All bus cycles
generated during exception processing are supervisor references, and all stack accesses
use the active supervisor stack pointer.
4.1.2 User Privilege Level
The user level is the lower privilege level. The privilege level is determined by the S bit of
the status register; if the S bit is clear, the processor executes instructions at the user
privilege level.
Most instructions execute at either privilege level, but some instructions that have important
system effects are privileged and can only be executed at the supervisor level. For instance,
user programs are not allowed to execute the STOP instruction or the RESET instruction.
To prevent a user program from entering the supervisor privilege level, except in a controlled
manner, instructions that can alter the S bit in the status register are privileged. The TRAP
#n instruction provides controlled access to operating system services for user programs.
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