Bus Operation
MOTOROLA MC68030 USER’S MANUAL 7-31
Each of the bus cycles is defined as a succession of states. These states apply to the bus
operation and are different from the processor states described in Section 4 Processing
States. The clock cycles used in the descriptions and timing diagrams of data transfer
cycles are independent of the clock frequency. Bus operations are described in terms of
external bus states.
7.3.1 Asynchronous Read Cycle
During a read cycle, the processor receives data from a memory, coprocessor, or peripheral
device. If the instruction specifies a long-word operation, the MC68030 attempts to read four
bytes at once. For a word operation, it attempts to read two bytes at once, and for a byte
operation, one byte. For some operations, the processor requests a three-byte transfer. The
processor properly positions each byte internally. The section of the data bus from which
each byte is read depends on the operand size, address signals (A0–A1), CIIN
and CIOUT,
whether the internal caches are enabled, and the port size. Refer to 7.2.1 Dynamic Bus
Sizing, 7.2.2 Misaligned Operands, and 7.2.6 Cache Filling for more information on
dynamic bus sizing, misaligned operands, and cache interactions.
Figure 7-19 is a flowchart of an asynchronous long-word read cycle. Figure 7-20 is a
flowchart of a byte read cycle. The following figures show functional read cycle timing
diagrams specified in terms of clock periods. Figure 7-21 corresponds to byte and word read
cycles from a 32-bit port. Figure 7-22 corresponds to a long-word read cycle from an 8-bit
port. Figure 7-23 also applies to a long-word read cycle, but from a 16-bit port.
State 0
The read cycle starts in state 0 (S0). The processor drives ECS
low, indicating the
beginning of an external cycle. When the cycle is the first external cycle of a read operand
operation, operand cycle start (OCS
) is driven low at the same time. During S0, the
processor places a valid address on A0–A31 and valid function codes on FC0–FC2. The
function codes select the address space for the cycle. The processor drives R/W
high for
a read cycle and drives DBEN
inactive to disable the data buffers. SIZ0–SIZ1 become
valid, indicating the number of bytes requested to be transferred. CIOUT
also becomes
valid, indicating the state of the MMU CI bit in the address translation descriptor or in the
appropriate TTx register.
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