Motorola MC68030 User Manual

Data Organization and Addressing Capabilities
MOTOROLA MC68030 USER’S MANUAL 2-39
In this case, after either a push or pull operation, register An points to the next available
space on the stack. This is illustrated as:
2.8.3 Queues
The user can implement queues with the address register indirect with postincrement or
predecrement addressing modes. Using a pair of address registers (who of A0–A6), the user
can implement a queue which is filled either from high to low memory or from low to high
memory. Two registers are used because queues are pushed from one end and pulled from
the other. One register, An, contains the "put'' pointer; the other, Am, the "get'' pointer.
To implement growth of the queue from low to high memory, use:
(An)+ to put data into the queue,
(Am)+ to get data from the queue.
After a "put'' operation, the "put'' address register points to the next available space in the
queue, and the unchanged "get'' address register points to the next item to be removed from
the queue. After a "get'' operation, the "get'' address register points to the next item to be
removed from the queue, and the unchanged "put'' address register points to the next
available space in the queue. This is illustrated as:
To implement the queue as a circular buffer, the relevant address register should be
checked and adjusted, if necessary, before performing the "put'' or "get'' operation. The
address register is adjusted by subtracting the buffer length (in bytes) from the register.
LOW MEMORY
TOP OF STACK
HIGH MEMORY
An
BOTTOM OF STACK
(FREE)
GET (Am) +
LOW MEMORY
(FREE)
HIGH MEMORY
LAST GET (FREE)
LAST PUT
NEXT GET
PUT (An) +

Motorola MC68030 Specifications

General

Brand	Motorola
Model	MC68030
Category	Computer Hardware
Language	English

Summary

MOTOROLA MC68030 USER'S MANUAL

PREFACE

Provides an overview of the MC68030 User's Manual, its audience, and structure.

SECTION 1 INTRODUCTION

Introduces the MC68030 microprocessor, its features, and architecture.

1.1 FEATURES

Details the key features and capabilities of the MC68030 microprocessor.

1.4 DATA TYPES AND ADDRESSING MODES

1.7 THE MEMORY MANAGEMENT UNIT

Details the MMU's role in virtual memory and address translation.

1.9 THE CACHE MEMORIES

SECTION 2 DATA ORGANIZATION AND ADDRESSING CAPABILITIES

2.2 ORGANIZATION OF DATA IN REGISTERS

2.4 ADDRESSING MODES

Covers the various addressing modes for accessing operands.

SECTION 3 INSTRUCTION SET SUMMARY

3.2 INSTRUCTION SUMMARY

Categorizes and summarizes the MC68030 instructions.

SECTION 4 PROCESSING STATES

4.1 PRIVILEGE LEVELS

4.3 EXCEPTION PROCESSING

Details exception handling, vector table, and stack frames.

SECTION 5 SIGNAL DESCRIPTION

5.7 CACHE CONTROL SIGNALS

SECTION 6 ON-CHIP CACHE MEMORIES

6.1 ON-CHIP CACHE ORGANIZATION AND OPERATION

6.1.1 Instruction Cache

6.1.2 Data Cache

6.3 CACHE CONTROL

SECTION 7 BUS OPERATION

7.1 BUS TRANSFER SIGNALS

7.2 DATA TRANSFER MECHANISM

7.3 DATA TRANSFER CYCLES

Defines signals for data transfer and describes read, write, and RMW cycles.

7.3.1 Asynchronous Read Cycle

7.3.2 Asynchronous Write Cycle

7.3.7 Burst Operation Cycles

7.5 BUS EXCEPTION CONTROL CYCLES

Covers DSACKx, STERM, AVEC assertion requirements and MMU errors.

7.5.1 Bus Errors

7.7 BUS ARBITRATION

Describes bus arbitration protocol for single bus master operation.

7.8 RESET OPERATION

Describes system and processor reset mechanisms.