Signal Description
MOTOROLA
MC68030 USER’S MANUAL
5-5
5.6 BUS CONTROL SIGNALS
The following signals control synchronous bus transfer operations for the MC68030.
5.6.1 Operand Cycle Start (OCS
)
This output signal indicates the beginning of the first external bus cycle for an instruction
prefetch or a data operand transfer. OCS
is not asserted for subsequent cycles that are
performed due to dynamic bus sizing or operand misalignment.
7.1.1 Bus Control Signals
for information about the relationship of OCS
to bus operation.
5.6.2 External Cycle Start (ECS
)
This output signal indicates the beginning of a bus cycle of any type.
7.1.1 Bus Control
Signals
for information about the relationship of ECS
to bus operation.
5.6.3 Read/Write (R/W
)
This three-state output signal defines the type of bus cycle. A high level indicates a read
cycle; a low level indicates a write cycle. Refer to
7.1.1 Bus Control Signals
for information
about the relationship of R/W
to bus operation.
5.6.4 Read-Modify-Write Cycle (RMC
)
This three-state output signal identifies the current bus cycle as part of an indivisible read-
modify-write operation; it remains asserted during all bus cycles of the read-modify-write
operation. Refer to
7.1.1 Bus Control Signals
for information about the relationship of RMC
to bus operation.
5.6.5 Address Strobe (AS
)
This three-state output indicates that a valid address is on the address bus. The function
code, size, and read/write signals are also valid when AS
is asserted. Refer to
7.1.3
Address Strobe
for information about the relationship of AS
to bus operation.
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