Motorola MC68030 User Manual

Bus Operation
7-98 MC68030 USER’S MANUAL MOTOROLA
7.7 BUS ARBITRATION
The bus design of the MC68030 provides for a single bus master at any one time: either the
processor or an external device. One or more of the external devices on the bus can have
the capability of becoming bus master. Bus arbitration is the protocol by which an external
device becomes bus master; the bus controller in the MC68030 manages the bus arbitration
signals so that the processor has the lowest priority. External devices that need to obtain the
bus must assert the bus arbitration signals in the sequences described in the following
paragraphs. Systems having several devices that can become bus master require external
circuitry to assign priorities to the device so that, when two or more external devices attempt
to become bus master at the same time, the one having the highest priority becomes bus
master first. The sequence of the protocol is:
1. An external device asserts the bus request signal.
2. The processor asserts the bus grant signal to indicate that the bus will become avail-
able at the end of the current bus cycle.
3. The external device asserts the bus grant acknowledge signal to indicate that it has
assumed bus mastership.
BR
may be issued any time during a bus cycle or between cycles. BG is asserted in
response to BR
; it is usually asserted as soon as BR has been synchronized and
recognized, except when the MC68030 has made an internal decision to execute a bus
cycle. Then, the assertion of BG
is deferred until the bus cycle has begun. Additionally, BG
is not asserted until the end of a read-modify-write operation (when RMC
is negated) in
response to a BR
signal. When the requesting device receives BG and more than one
external device can be bus master, the requesting device should begin whatever arbitration
is required. The external device asserts BGACK
when it assumes bus mastership and
Figure 7-58. Bus Synchronization Example
S0 Sw
EXTERNAL WRITE
WRITE TO D. CACHE D. CACHE READ
MOVE. L D0, (A0)
NOP PREVENTS EXECUTION OF SUBSEQUENT
INSTRUCTIONS UNTIL MOVE. L D0, (A0)
WRITE CYCLE COMPLETES
MOVE . L (A0), D1

Motorola MC68030 Specifications

General

Brand	Motorola
Model	MC68030
Category	Computer Hardware
Language	English

Summary

MOTOROLA MC68030 USER'S MANUAL

PREFACE

Provides an overview of the MC68030 User's Manual, its audience, and structure.

SECTION 1 INTRODUCTION

Introduces the MC68030 microprocessor, its features, and architecture.

1.1 FEATURES

Details the key features and capabilities of the MC68030 microprocessor.

1.4 DATA TYPES AND ADDRESSING MODES

1.7 THE MEMORY MANAGEMENT UNIT

Details the MMU's role in virtual memory and address translation.

1.9 THE CACHE MEMORIES

SECTION 2 DATA ORGANIZATION AND ADDRESSING CAPABILITIES

2.2 ORGANIZATION OF DATA IN REGISTERS

2.4 ADDRESSING MODES

Covers the various addressing modes for accessing operands.

SECTION 3 INSTRUCTION SET SUMMARY

3.2 INSTRUCTION SUMMARY

Categorizes and summarizes the MC68030 instructions.

SECTION 4 PROCESSING STATES

4.1 PRIVILEGE LEVELS

4.3 EXCEPTION PROCESSING

Details exception handling, vector table, and stack frames.

SECTION 5 SIGNAL DESCRIPTION

5.7 CACHE CONTROL SIGNALS

SECTION 6 ON-CHIP CACHE MEMORIES

6.1 ON-CHIP CACHE ORGANIZATION AND OPERATION

6.1.1 Instruction Cache

6.1.2 Data Cache

6.3 CACHE CONTROL

SECTION 7 BUS OPERATION

7.1 BUS TRANSFER SIGNALS

7.2 DATA TRANSFER MECHANISM

7.3 DATA TRANSFER CYCLES

Defines signals for data transfer and describes read, write, and RMW cycles.

7.3.1 Asynchronous Read Cycle

7.3.2 Asynchronous Write Cycle

7.3.7 Burst Operation Cycles

7.5 BUS EXCEPTION CONTROL CYCLES

Covers DSACKx, STERM, AVEC assertion requirements and MMU errors.

7.5.1 Bus Errors

7.7 BUS ARBITRATION

Describes bus arbitration protocol for single bus master operation.

7.8 RESET OPERATION

Describes system and processor reset mechanisms.