Bus Operation
7-84 MC68030 USER’S MANUAL MOTOROLA
EXAMPLE B:
A system uses error detection and correction on RAM contents. The designer may:
1. Delay DSACK
x until data is verified; assert BERR and HALT simultaneously to indi-
cate to the processor to automatically retry the error cycle (case 5) or, if data is valid,
assert DSACK
x (case 1).
2. Delay DSACKx
until data is verified and assert BERR with or without DSACKx if data
is in error (case 3). This initiates exception processing for software handling of the
condition.
3. Return DSACKx
prior to data verification. If data is invalid, BERR is asserted on the
next clock cycle (case 4). This initiates exception processing for software handling of
the condition.
4. Return DSACKx
prior to data verification; if data is invalid, assert BERR and HALT on
the next clock cycle (case 6). The memory controller can then correct the RAM prior
to or during the automatic retry.
7.5.1 Bus Errors
The bus error signal can be used to abort the bus cycle and the instruction being executed.
BERR
takes precedence over DSACKx or STERM provided it meets the timing constraints
described in MC68030EC/D,
MC68030 Electrical Specifications
. If BERR does not meet
these constraints, it may cause unpredictable operation of the MC68030. If BERR
remains
asserted into the next bus cycle, it may cause incorrect operation of that cycle.
When the bus error signal is issued to terminate a bus cycle, the MC68030 may enter
exception processing immediately following the bus cycle, or it may defer processing the
exception. The instruction prefetch mechanism requests instruction words from the bus
controller and the instruction cache before it is ready to execute them. If a bus error occurs
on an instruction fetch, the processor does not take the exception until it attempts to use that
instruction word. Should an intervening instruction cause a branch or should a task switch
occur, the bus error exception does not occur.
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