Motorola MC68030 User Manual

Data Organization and Addressing Capabilities
2-38 MC68030 USER’S MANUAL MOTOROLA
2.8.2 User Program Stacks
The user can implement stacks with the address register indirect with postincrement and
predecrement addressing modes. With address register An (n = 0–6), the user can
implement a stack that is filled wither from high to low memory or from low to high memory.
Important considerations are:
• Use the predecrement mode to decrement the register before its contents are used as
the pointer to the stack.
• Use the postincrement mode to increment the register after its contents are used as the
pointer to the stack.
• Maintain the stack pointer correctly when byte, word, and long-word items are mixed in
these stacks.
To implement stack growth from high to low memory, use:
–(An) to push data on the stack,
(An)+ to pull data from the stack.
For this type of stack, after either a push or a pull operation, register An points to the top item
on the stack. This is illustrated as:
To implement stack growth from low to high memory, use:
(An)+ to push data on the stack,
–An to pull data from the stack.
An
LOW MEMORY
(FREE)
TOP OF STACK
BOTTOM OF STACK
HIGH MEMORY

Motorola MC68030 Specifications

General

Brand	Motorola
Model	MC68030
Category	Computer Hardware
Language	English

Summary

MOTOROLA MC68030 USER'S MANUAL

PREFACE

Provides an overview of the MC68030 User's Manual, its audience, and structure.

SECTION 1 INTRODUCTION

Introduces the MC68030 microprocessor, its features, and architecture.

1.1 FEATURES

Details the key features and capabilities of the MC68030 microprocessor.

1.4 DATA TYPES AND ADDRESSING MODES

1.7 THE MEMORY MANAGEMENT UNIT

Details the MMU's role in virtual memory and address translation.

1.9 THE CACHE MEMORIES

SECTION 2 DATA ORGANIZATION AND ADDRESSING CAPABILITIES

2.2 ORGANIZATION OF DATA IN REGISTERS

2.4 ADDRESSING MODES

Covers the various addressing modes for accessing operands.

SECTION 3 INSTRUCTION SET SUMMARY

3.2 INSTRUCTION SUMMARY

Categorizes and summarizes the MC68030 instructions.

SECTION 4 PROCESSING STATES

4.1 PRIVILEGE LEVELS

4.3 EXCEPTION PROCESSING

Details exception handling, vector table, and stack frames.

SECTION 5 SIGNAL DESCRIPTION

5.7 CACHE CONTROL SIGNALS

SECTION 6 ON-CHIP CACHE MEMORIES

6.1 ON-CHIP CACHE ORGANIZATION AND OPERATION

6.1.1 Instruction Cache

6.1.2 Data Cache

6.3 CACHE CONTROL

SECTION 7 BUS OPERATION

7.1 BUS TRANSFER SIGNALS

7.2 DATA TRANSFER MECHANISM

7.3 DATA TRANSFER CYCLES

Defines signals for data transfer and describes read, write, and RMW cycles.

7.3.1 Asynchronous Read Cycle

7.3.2 Asynchronous Write Cycle

7.3.7 Burst Operation Cycles

7.5 BUS EXCEPTION CONTROL CYCLES

Covers DSACKx, STERM, AVEC assertion requirements and MMU errors.

7.5.1 Bus Errors

7.7 BUS ARBITRATION

Describes bus arbitration protocol for single bus master operation.

7.8 RESET OPERATION

Describes system and processor reset mechanisms.