Bus Operation
MOTOROLA MC68030 USER’S MANUAL 7-71
The CPU space type is encoded on A16-A19 during a CPU space operation and indicates
the function that the processor is performing. On the MC68030, three of the encodings are
implemented as shown in Figure 7-42. All unused values are reserved by Motorola for future
additional CPU space types.
7.4.1 Interrupt Acknowledge Bus Cycles
When a peripheral device signals the processor (with the IPL0–IPL2 signals) that the device
requires service, and the internally synchronized value on these signals indicates a higher
priority than the interrupt mask in the status register (or that a transition has occurred in the
case of a level 7 interrupt), the processor makes the interrupt a pending interrupt. Refer to
8.1.9 Interrupt Exceptions for details on the recognition of interrupts.
The MC68030 takes an interrupt exception for a pending interrupt within one instruction
boundary (after processing any other pending exception with a higher priority). The following
paragraphs describe the various kinds of interrupt acknowledge bus cycles that can be
executed as part of interrupt exception processing.
Figure 7-42. MC68030 CPU Space Address Encoding
1 1 1
1 1 1
1 1 1
BREAKPOINT
ACKNOWLEDGE
COPROCESSOR
COMM.
INTERRUPT
ACKNOWLEDGE
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 CPID 0 0 0 0 0 0 0 0 CP REG
15 13 4 0
31031
31
BKPT # 0 0
31
420
0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 162320
FUNCTION
CODE
ADDRESS BUS
CPU SPACE
TYPE FIELD
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