Bus Operation
MOTOROLA MC68030 USER’S MANUAL 7-85
The bus error signal is recognized during a bus cycle in any of the following cases:
• DSACKx
(or STERM) and HALT are negated and BERR is asserted.
• HALT
and BERR are negated and DSACKx is asserted. BERR is then asserted within
one clock cycle (HALT
remains negated).
• BERR
is asserted and recognized on the next falling clock edge following the rising
clock edge on which STERM
is asserted and recognized (HALT remains negated).
When the processor recognizes a bus error condition, it terminates the current bus cycle in
the normal way. Figure 7-49 shows the timing of a bus error for the case in which neither
DSACK
x nor STERM is asserted. Figure 7-50 shows the timing for a bus error that is
asserted after DSACKx
. Exceptions are taken in both cases. (Refer to 8.1.2 Bus Error
Exception for details of bus error exception processing.) When BERR
is asserted during a
read cycle that supplies data to either on-chip cache, the data in the cache is marked invalid.
However, when a write cycle that writes data into the data cache results in an externally
generated bus error, the data in the cache is not marked invalid.
In the second case, where BERR
is asserted after DSACKx is asserted, BERR must be
asserted within specification #48 (refer to MC68030EC/D,
MC68030 Electrical
Specifications
) for purely asynchronous operation, or it must be asserted and remain stable
during the sample window, defined by specifications #27A and #47B, around the next falling
edge of the clock after DSACKx
is recognized. If BERR is not stable at this time, the
processor may exhibit erratic behavior. BERR
has priority over DSACKx. In this case, data
may be present on the bus, but may not be valid. This sequence may be used by systems
that have memory error detection and correction logic and by external cache memories.
The assertion of BERR
described in the third case (recognized after STERM) has
requirements similar to those described in the preceding paragraph. BERR
must be stable
throughout the sample window for the next falling edge of the clock, as defined by
specifications #27A and #28A. Figure 7-51 shows the timing for this case.
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