Processing States
MOTOROLA
MC68030 USER’S MANUAL
4-5
4.2 ADDRESS SPACE TYPES
The processor specifies a target address space for every bus cycle with the function code
signals according to the type of access required. In addition to distinguishing between
supervisor/user and program/data, the processor can identify special processor cycles,
such as the interrupt acknowledge cycle, and the memory management unit can control
accesses and translate addresses appropriately. Table 4-1 lists the types of accesses
defined for the MC68030 and the corresponding values of function codes FC0–FC2.
*Address space 3 is reserved for user definition; whereas, 0 and 4
are reserved for future use by Motorola.
The memory locations of user program and data accesses are not predefined. Neither are
the locations of supervisor data space. During reset, the first two long words beginning at
memory location zero in the supervisor program space are used for processor initialization.
No other memory locations are explicitly defined by the MC68030.
A function code of $7 ([FC2:FC0] = 111) selects the CPU address space. This is a special
address space that does not contain instructions or operands but is reserved for special
processor functions. The processor uses accesses in this space to communicate with
external devices for special purposes. For example, all M68000 processors use the CPU
space for interrupt acknowledge cycles. The MC68020 and MC68030 also generate CPU
space accesses for breakpoint acknowledge and coprocessor operations.
Supervisor programs can use the MOVES instruction to access all address spaces,
including the user spaces and the CPU address space. Although the MOVES instruction can
be used to generate CPU space cycles, this may interfere with proper system operation.
Thus, the use of MOVES to access the CPU space should be done with caution.
Table 4-1. Address Space Encodings
FC2 FC1 FC0 Address Space
0 0 0 (Undefined, Reserved)*
0 0 1 User Data Space
0 1 0 User Program Space
0 1 1 (Undefined, Reserved)*
1 0 0 (Undefined, Reserved)*
1 0 1 Supervisor Data Space
1 1 0 Supervisor Program Space
1 1 1 CPU Space
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