Bus Operation
MOTOROLA MC68030 USER’S MANUAL 7-77
7.5 BUS EXCEPTION CONTROL CYCLES
The MC68030 bus architecture requires assertion of either DSACKx or STERM from an
external device to signal that a bus cycle is complete. DSACKx
, STERM, or AVEC is not
asserted if:
• The external device does not respond.
• No interrupt vector is provided.
• Various other application-dependent errors occur.
External circuitry can provide BERR
when no device responds by asserting DSACKx,
STERM, or AVEC within an appropriate period of time after the processor asserts AS. This
allows the cycle to terminate and the processor to enter exception processing for the error
condition.
The MMU can also detect an internal bus error. This occurs when the processor attempts to
access an address in a protected area of memory (a user program attempts to access
supervisor data, for example) or after the MMU receives a bus error while searching the
address table for an address translation description.
Figure 7-46. Breakpoint Operation Flow
1) PLACE REPLACEMENT OPCODE ON DATA
BUS
2) ASSERT DATA TRANSFER AND SIZE
ACKNOWLEDGE (DSACKx) SYNCHRONOUS
TERMINATION (STERM)
OR
1) ASSERT BUS ERRROR (BERR) TO INITIATE
EXCEPTION PROCESSING
CONTROLLER
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON A19-A16
4) PLACE BREAKPOINT NUMBER ON A4-A2
5) SET SIZE TO WORD
6) ASSERT ADDRESS STROBE (AS) AND DATA
STROBE (DS)
BREAKPOINT ACKNOWLEDGE
1) PLACE LATCHED DATA IN INSTRUCTION
PIPELINE
2) CONTINUE PROCESSING
1) INITIATE ILLEGAL INSTRUCTION PROCESSING
SLAVE NEGATES DSACKx, STERM OR BERR
EXTERNAL DEVICE
IF DSACKx OR STERM
1) LATCH DATA
2) NEGATE AS AND DS
3) GO TO A
IF BERR ASSERTED:
1) NEGATE AS AND DS
2) GO TO B A B
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