Motorola MC68030 User Manual

Bus Operation
7-93 MC68030 USER’S MANUAL MOTOROLA
7.5.3 Halt Operation
When HALT is asserted and BERR is not asserted, the MC68030 halts external bus activity
at the next bus cycle boundary. HALT
by itself does not terminate a bus cycle. Negating and
reasserting HALT
in accordance with the correct timing requirements provides a single-step
(bus cycle to bus cycle) operation. The HALT
signal affects external bus cycles only; thus,
a program that resides in the instruction cache and performs no data writes (or reads that
miss in the data cache) may continue executing, unaffected by the HALT
signal.
Figure 7-55. Synchronous Late Retry
A31-A0
FC2-FC0
R/W
ECS
OCS
CLK
S0 S2
S1
AS
DS
STERM
SIZ1–SIZ0
S3 S0 S1 S2 S3
D31–D0
BERR
HALT
READ CYCLE
RETRY SIGNALED
HALT RETRY CYCLE

Motorola MC68030 Specifications

General

Brand	Motorola
Model	MC68030
Category	Computer Hardware
Language	English