Bus Operation
MOTOROLA MC68030 USER’S MANUAL 7-61
State 7
The processor negates AS
(and DS, if necessary) during S7. It holds the address and
data valid during S7 to simplify memory interfaces. R/W
and FC0–FC2 also remain valid
throughout S7.
If more than one write cycle is required, S8-S11 are repeated for each write cycle.
The external device must negate STERM
within two clock periods after asserting it, or the
processor may inadvertently use STERM
for the next bus cycle.
7.3.7 Burst Operation Cycles
The MC68030 supports a burst mode for filling the on-chip instruction and data caches.
The MC68030 provides a set of handshake control signals for the burst mode. When a miss
occurs in one of the caches, the MC68030 initiates a bus cycle to obtain the required data
or instruction stream fetch. If the data or instruction can be cached, the MC68030 attempts
to fill a cache entry. Depending on the alignment for a data access, the MC68030 may
attempt to fill two cache entries. The processor may also assert CBREQ
to request a burst
fill operation. That is, the processor can fill additional entries in the line. The MC68030 allows
a burst of as many as four long words.
The mechanism that asserts the CBREQ
signal for burstable cache entries is enabled by
the data burst enable (DBE
) and instruction burst enable (IBE) bits of the cache control
register (CACR
) for the data and instruction caches, respectively. Either of the following
conditions cause the MC68030 to initiate a cache burst request (and assert CBREQ
) for a
cachable read cycle:
• The logical address and function code signals of the current instruction or data fetch do
not match the indexed tag field in the respective instruction or data cache.
• All four long words corresponding to the indexed tag in the appropriate cache are
marked invalid.
However, the MC68030 does not assert CBREQ
during the first portion of a misaligned
access if the remainder of the access does not correspond to the same cache line. Refer to
6.1.3.1 Single Entry Mode for details.
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