Signal Description
MOTOROLA
MC68030 USER’S MANUAL
5-7
5.7 CACHE CONTROL SIGNALS
The following signals relate to the on-chip caches.
5.7.1 Cache Inhibit Input (CIIN
)
This input signal prevents data from being loaded into the MC68030 instruction and data
caches. It is a synchronous input signal and is interpreted on a bus-cycle-by-bus-cycle
basis. CIIN
is ignored during all write cycles. Refer to
6.1 On-Chip Cache Organization
and Operation
for information on the relationship of CIIN to the on-chip caches.
5.7.2 Cache Inhibit Output (CIOUT
)
This three-state output signal reflects the state of the CI bit in the address translation cache
entry for the referenced logical address, indicating that an external cache should ignore the
bus transfer. When the referenced logical address is within an area specified for transparent
translation, the CI bit of the appropriate transparent translation register controls the state of
CIOUT
. Refer to
Section 9 Memory Management Unit
for more information about the
address translation cache and transparent translation. Also, refer to
Section 6 On-Chip
Cache Memories
for the effect of CIOUT
on the internal caches.
5.7.3 Cache Burst Request (CBREQ
)
This three-state output signal requests a burst mode operation to fill a line in the instruction
or data cache. Refer to
6.1.3 Cache Filling
for filling information and
7.3.7 Burst Operation
Cycles
for bus cycle information pertaining to burst mode operations.
5.7.4 Cache Burst Acknowledge (CBACK
)
This input signal indicates that the accessed device can operate in the burst mode and can
supply at least one more long word for the instruction or data cache. Refer to
7.3.7 Burst
Operation Cycles
for information about burst mode operation.
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