Motorola MC68030 User Manual

Data Organization and Addressing Capabilities
MOTOROLA MC68030 USER’S MANUAL 2-17
2.4.13 Program Counter Indirect with Index (Base Displacement) Mode
This mode is similar to the address register indirect with index (base displacement) mode
described in 2.4.8 Address Register Indirect with Index (Base Displacement) Mode , but
the PC is used as the base register. It requires an index register indicator and an optional
16- or 32-bit sign-extended base displacement. The operand is in memory. The address of
the operand is the sum of the contents of the PC, the scaled contents of the sign-extended
index register, and the base displacement. The value of the PC is the address of the first
extension word. The reference is a program space reference and is only allowed for reads
(refer to 4.2 Address Space Types ).
In this mode, the PC, the index register, and the displacement are all optional. However, the
user must supply the assembler notation "ZPC'' (zero value is taken for the PC) to indicate
that the PC is not used. This allows the user to access the program space without using the
PC in calculating the effective address. The user can access the program space with a data
register indirect access by placing ZPC in the instruction and specifying a data register (Dn)
as the index register.
31 0
31 0
31 0
31 0
EA = (PC) + (Xn) + bd
(bd, PC, Xn. SIZE*SCALE)
111
011
+
OPERANDMEMORY ADDRESS:
NUMBER OF EXTENSION WORDS:
GENERATION:
ASSEMBLER SYNTAX:
MODE:
REGISTER:
PROGRAM COUNTER:
SIGN-EXTENDED VALUE
SCALE VALUE
+
X
BASE DISPLACEMENT:
INDEX REGISTER
SCALE:
1, 2 OR 3
ADDRESS OF EXTENSION WORD
SIGN-EXTENDED VALUE
07

Motorola MC68030 Specifications

General

Brand	Motorola
Model	MC68030
Category	Computer Hardware
Language	English

Summary

MOTOROLA MC68030 USER'S MANUAL

PREFACE

Provides an overview of the MC68030 User's Manual, its audience, and structure.

SECTION 1 INTRODUCTION

Introduces the MC68030 microprocessor, its features, and architecture.

1.1 FEATURES

Details the key features and capabilities of the MC68030 microprocessor.

1.4 DATA TYPES AND ADDRESSING MODES

1.7 THE MEMORY MANAGEMENT UNIT

Details the MMU's role in virtual memory and address translation.

1.9 THE CACHE MEMORIES

SECTION 2 DATA ORGANIZATION AND ADDRESSING CAPABILITIES

2.2 ORGANIZATION OF DATA IN REGISTERS

2.4 ADDRESSING MODES

Covers the various addressing modes for accessing operands.

SECTION 3 INSTRUCTION SET SUMMARY

3.2 INSTRUCTION SUMMARY

Categorizes and summarizes the MC68030 instructions.

SECTION 4 PROCESSING STATES

4.1 PRIVILEGE LEVELS

4.3 EXCEPTION PROCESSING

Details exception handling, vector table, and stack frames.

SECTION 5 SIGNAL DESCRIPTION

5.7 CACHE CONTROL SIGNALS

SECTION 6 ON-CHIP CACHE MEMORIES

6.1 ON-CHIP CACHE ORGANIZATION AND OPERATION

6.1.1 Instruction Cache

6.1.2 Data Cache

6.3 CACHE CONTROL

SECTION 7 BUS OPERATION

7.1 BUS TRANSFER SIGNALS

7.2 DATA TRANSFER MECHANISM

7.3 DATA TRANSFER CYCLES

Defines signals for data transfer and describes read, write, and RMW cycles.

7.3.1 Asynchronous Read Cycle

7.3.2 Asynchronous Write Cycle

7.3.7 Burst Operation Cycles

7.5 BUS EXCEPTION CONTROL CYCLES

Covers DSACKx, STERM, AVEC assertion requirements and MMU errors.

7.5.1 Bus Errors

7.7 BUS ARBITRATION

Describes bus arbitration protocol for single bus master operation.

7.8 RESET OPERATION

Describes system and processor reset mechanisms.