Rigol DS2302A User Manual

RIGOL Chapter 7 Digital Channel
7-6 MSO2000A/DS2000A User’s Guide
To Use the Digital Bus
Users can display the three groups of channels (D7-D0, D15-D8 and D15-D0) as
digital buses according to their needs. Each bus value will be displayed at the bottom
of the screen in data or graph form. You can create up to 2 buses.
Press LA  Bus to enter the digital bus setting menu.
 Press Bus to select “BUS1” or “BUS2”.
 Press BusStatus to turn on or off the digital bus.
 Press Sel CH to set the corresponding channels of BUS1 or BUS2 to D7-D0,
D15-D8 or D15-D0.
 Press Endian to set the bus endian to “Normal (D0 locates at the least
significant bit)” or “Invert (D0 locates at the most significant bit)” and the
default is “Normal”.
 Press RefClock to select any channel of D0-D15 or CH1-CH2 as the reference
clock of the bus. Selecting “None” means no reference clock will be used.
When CH1 or CH2 is selected to be the reference clock, you can press
Threshold and rotate the multifunction knob to set the threshold of the
clock channel, the range is from (-4*vertical scale - vertical position) to
(4*vertical scale - vertical position). Pressing down
can quickly reset the
threshold level of the clock channel to 0 V. When any channel of D0-D15 is
selected to be the reference clock, Threshold will be hidden automatically and
the threshold cannot be set.
 Press Slope to set the sample edge type of the reference clock to (rising
edge) or
(falling edge).
 Press Type to set the display mode of the digital bus to “Data” or “Graph”. In
data mode, the bus data is displayed; in graph mode, the oscilloscope displays
the level of the corresponding value of the bus data for easier observation of the
variation tendency of the bus values.
 Press Format to set the display format of the digital bus to Hex, Decimal, Binary
or ASCII.
 Press Jitter Reject to turn on the jitter rejection function. Jitter refers to the
short-term deviation of the signal relative to its ideal time position at certain
time point, as shown as T1 and T2 in
Figure 7-1. When no reference clock is
selected for the bus, the jump status of each channel would cause the variation
of the bus data and undesired data would be generated due to jitter when the
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Rigol DS2302A Specifications

General

Brand	Rigol
Model	DS2302A
Category	Test Equipment
Language	English