LMK04821
,
LMK04826
,
LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
www.ti.com
DCLKout0_DDLY_CNTL, DCLKout2_DDLY_CNTH, DCLKout2_DDLY_CNTL, DCLKout4_DDLY_CNTH,
DCLKout4_DDLY_CNTL, SYSREF_DDLY. ........................................................................................................................ 37
• Added = 1 in SYSREF Request .......................................................................................................................................... 38
• Changed step numbers in dynamic delay and references to steps to be correct, step 8 was duplicated .......................... 41
• Added note LMK04821 includes VCO1 divider on VCO1 output......................................................................................... 46
• Added note LMK04821 includes VCO1 divider on VCO1 output......................................................................................... 47
• Added R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read. ......................................................................................... 49
• Added If using LMK04821, program register 0x174 in Recommended Programming Sequence ...................................... 49
• Added SYSREF_CLKin0_MUX and VCO1_DIV to register map......................................................................................... 51
• Added CLKin_OVERRIDE bit to register map ..................................................................................................................... 52
• Changed from half shift to half step...................................................................................................................................... 57
• Changed definition of SDCLKoutY_DDLY value of 0 from Reserved to Bypass................................................................. 57
• Changed from Sets the polarity of SYSREF clocks to Sets the polarity of clock on SDCLKoutY when device clock
output is selected with SDCLKoutY_MUX............................................................................................................................ 60
• Changed Sets the polarity of the device clocks to Sets the polarity of the device clocks from the DCLKoutX outputs ...... 60
• Added LMK04821 DCLKoutX_FMT power on reset values as powerdown......................................................................... 60
• Changed from SYSREF to SYSREF Divider in Source column of Register 0x13F ............................................................ 64
• Changed reserved to Off for CLKin1_OUT_MUX ............................................................................................................... 69
• Changed reserved to Off for CLKin0_OUT_MUX. .............................................................................................................. 69
• Added CLKin_OVERRIDE bit .............................................................................................................................................. 76
• Added LMK04821 register 0x174 for VCO1_DIV................................................................................................................. 91
• Deleted LMK04828 from Core line .................................................................................................................................... 102
• Added VCO1 Icc including VCO1 Divider for LMK04821................................................................................................... 102
• Changed VCO1 Icc and power dissipated for LMK04828B/26B from 6 mA to 13.5 mA and 19.8 mW to 44.55 mW ....... 102
Changes from Revision AO (March 2013) to Revision AP Page
• Changed datasheet title from LMK04828 to LMK0482xB ...................................................................................................... 1
• Changed LMK04828 family to LMK04820 family ................................................................................................................... 1
• Changed image from LMK04828B to LMK0482xB ................................................................................................................ 1
• Added LMK04826 to Device Configuration Information table ................................................................................................ 6
• Changed - increased LMK04828B VCO0 max frequency from 2600 MHz to 2630 MHz ...................................................... 6
• Changed - expanded LMK04828B VCO1 frequency range from 2945 - 3005 MHz to 2920 MHz - 3080 MHz..................... 6
• Changed Thermal Information header from LMK04828B to LMK0482xB.............................................................................. 9
• Added LMK04826 VCO Range Specification....................................................................................................................... 13
• Changed - increased LMK04828B VCO0 max frequency from 2600 MHz to 2630 MHz .................................................... 13
• Changed - expanded LMK04828B VCO1 frequency range from 2945 - 3005 MHz to 2920 MHz - 3080 MHz................... 13
• Added LMK04826 K
VCO
specification ................................................................................................................................... 13
• Added clarification of LMK04828 specification vs LMK04826 specification for K
VCO
........................................................... 13
• Added LMK04826 noise floor data ....................................................................................................................................... 14
• Changed - clarified phase noise data section header.......................................................................................................... 15
• Added LMK04826 phase noise data .................................................................................................................................... 16
• Added LMK04826 jitter data................................................................................................................................................. 17
• Added LMK04826 f
CLKout-startup
spec ...................................................................................................................................... 19
• Added clarification of LMK04828 specification vs. LMK04826 specification for f
CLKout-startup
................................................. 19
• Added LMK04826B Phase Noise Performance Graph for VCO0 ........................................................................................ 24
• Added LMK04826B Phase Noise Performance Graph for VCO1 ........................................................................................ 24
• Added Added PLL2 loop filter bandwidth and phase margin info to plot ............................................................................. 25
4 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: LMK04821 LMK04826 LMK04828
To Next Page
Loading...
Need help?
General
