Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 161
UG482 (v1.9) December 19, 2016
RX Byte and Word Alignment
Figure 4-26 shows TX parallel data on the left side, and RX receiving recognizable parallel data
after comma alignment on the right side.
Enabling Comma Alignment
To enable the comma alignment block, the RXCOMMADETEN port is driven High.
RXCOMMADETEN is driven Low to bypass the block completely for minimum latency.
Configuring Comma Patterns
To set the comma pattern that the block searches for in the incoming data stream, the
ALIGN_MCOMMA_VALUE, ALIGN_PCOMMA_VALUE, and ALIGN_COMMA_ENABLE
attributes are used. The comma lengths depend on RX_DATA_WIDTH (see Table 4-47, page 216).
Figure 4-27 shows how the ALIGN_COMMA_ENABLE masks each of the comma values to allow
partial pattern matching.
Figure 4-28 shows how the commas are combined when ALIGN_COMMA_DOUBLE is TRUE.
X-Ref Target - Figure 4-26
Figure 4-26: Parallel Data View of Comma Alignment
TX Parallel Data RX Parallel Data
Data0
Comma
Data1
Data2
Non-aligned
Data
Comma
Data1
Data2
Time
UG482_c4_15_110911
X-Ref Target - Figure 4-27
Figure 4-27: Comma Pattern Masking
X-Ref Target - Figure 4-28
Figure 4-28: Extended Comma Pattern Definition
0101111100
xxx1111100
0001111111
ALIGN_MCOMMA_VALUE
or
ALIGN_PCOMMA_VALUE
Pattern Required for
Comma Detection
(x = Don’t Care)
ALIGN_COMMA_ENABLE
UG482_c4_16_111011
ALIGN_MCOMMA_VALUE ALIGN_PCOMMA_VALUE
UG482_c4_17_111011
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English