Xilinx 7 Series User Manual

126 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
9. RX Byte and Word Alignment, page 161
10. RX 8B/10B Decoder, page 170
11. RX Buffer Bypass, page 174
12. RX Elastic Buffer, page 187
13. RX Clock Correction, page 191
14. RX Channel Bonding, page 198
15. RX Gearbox, page 207
16. FPGA RX Interface, page 214
RX Analog Front End
Functional Description
The RX analog front end (AFE) is a high-speed current-mode input differential buffer (see
Figure 4-1). It has these features:
• Configurable RX termination voltage
• Calibrated termination resistors
X-Ref Target - Figure 4-2
Figure 4-2: RX Analog Front End
+
–
+
–
FPGABoard
ACJTAG RX
ACJTAG RX
50Ω
50Ω
MGTAVTT Programmable
GND
FLOAT
MGTAVTT
MGTAVTT
~100 nF
~100 nF
RX_CM_SEL[1:0]
UG482_c4_02_110911
RX_CM_TRIM[3:0]
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600