Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 11
UG482 (v1.9) December 19, 2016
Chapter 1
Transceiver and Tool Overview
Overview and Features
The 7 series FPGAs GTP transceiver is a power-efficient transceiver, supporting line rates between
500 Mb/s and 6.6 Gb/s. The GTP transceiver is highly configurable and tightly integrated with the
programmable logic resources of the FPGA. Table 1-1 summarizes the features by functional group
that support a wide variety of applications.
Table 1-1: 7 Series FPGAs Transceiver Features
Group Feature GTP GTX GTH
PCS 2-byte internal datapath x x x
4-byte internal datapath x x
8B/10B encoding and decoding x x x
64B/66B and 64B/67B support x x x
Comma detection and byte and word alignment x x x
PRBS generator and checker x x x
FIFO for clock correction and channel bonding x x x
Programmable FPGA logic interface x x x
PMA One shared LC tank PLL per Quad x x
One ring oscillator PLL per channel x x
Two shared ring oscillator PLLs per Quad x
Flexible reference clocking options x x x
Decision feedback equalization (DFE) x x
Power-efficient adaptive linear equalizer mode called the low-power mode (LPM) x x x
TX Pre-emphasis x x x
Beacon signaling for PCI Express® designs x x x
Out-of-band (OOB) signaling including COM signal support for Serial ATA (SATA)
designs
xxx
RX Margin Analysis x x x
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English