7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 9
UG482 (v1.9) December 19, 2016
Preface
About This Guide
Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to enable
a common design to scale across families for optimal power, performance, and cost. The Spartan®-7
family is the lowest density with the lowest cost entry point into the 7 series portfolio. The Artix®-7
family is optimized for highest performance-per-watt and bandwidth-per-watt for cost-sensitive,
high-volume applications. The Kintex®-7 family is an innovative class of FPGAs optimized for the
best price-performance. The Virtex®-7 family is optimized for highest system performance and
capacity. This guide serves as a technical reference describing the 7 series FPGAs GTP transceivers.
The 7 series FPGAs GTP transceivers user guide, part of an overall set of documentation on the
7 series FPGAs, is available on the Xilinx website at xilinx.com/documentation
.
In this document:
• 7 series FPGAs GTP transceiver channel is abbreviated as GTP transceiver.
• GTPE2_CHANNEL is the name of the instantiation primitive that instantiates one GTP
transceiver channel.
• GTPE2_COMMON is the name of the primitive that instantiates two ring oscillator PLLs
(PLL0 and PLL1).
• A Quad or Q is a cluster or set of four GTP transceiver channels, one GTPE2_COMMON
primitive, two differential reference clock pin pairs, and analog supply pins.
Guide Contents
This manual contains:
• Chapter 1, Transceiver and Tool Overview
• Chapter 2, Shared Features
• Chapter 3, Transmitter
• Chapter 4, Receiver
• Chapter 5, Board Design Guidelines
• Appendix A, Placement Information by Package
• Appendix B, Placement Information by Device
• Appendix C, 8B/10B Valid Characters
• Appendix D, DRP Address Map of the GTP Transceiver
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