Xilinx 7 Series User Manual

170 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
transceiver always receives the right-most bit first. Consequently, the 8B/10B decoder automatically
reverses the bit order of received data before decoding it. Decoded data is available on RXDATA
ports. Figure 4-33 shows data received by the GTP transceiver RX when RX_DATA_WIDTH = 20
or 40. Data is reconstructed into bytes and sent to the RXDATA interface after the 8B/10B decoder.
The number of bits used by RXDATA and corresponding byte orders are determined by
RX_DATA_WIDTH.
• Only use RXDATA[15:0] if RX_DATA_WIDTH = 20
• Use full RXDATA[31:0] if RX_DATA_WIDTH = 40
When the 8B/10B decoder is bypassed but RX_DATA_WIDTH is set to multiple of 10, 10-bit
characters are passed to the RX data interface with this format:
• The corresponding RXDISPERR represents the 9th bit
• The corresponding RXCHARISK represents the 8th bit
• The corresponding RXDATA byte represents the [7:0] bits
RX Running Disparity
Disparity check is performed and the decoder drives the corresponding RXDISPERR High when the
data byte on RXDATA arrives with the wrong disparity. In addition to disparity errors, the 8B/10B
decoder detects 20-bit out-of-table error codes. The decoder drives the RXNOTINTABLE port High
when decoder is enabled but a received 10-bit character cannot be mapped into a valid 8B/10B
character listed in Appendix C, 8B/10B Valid Characters. The non-decoded 10-bit character is piped
out of the decoder through the RX data interface with this format:
X-Ref Target - Figure 4-33
Figure 4-33: 8B/10B Decoder Bit and Byte Order
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1 G1 F1 E1 D1 C1 B1 A1 H0 G0 F0 E0 D0 C0 B0 A0
H3 G3 F3 E3 D3 C3 B3 A3 H2 G2 F2 E2 D2 C2 B2 A2 H1 G1 F1 E1 D1 C1 B1 A1 H0 G0 F0 E0 D0 C0 B0 A0
j1 h1 g1 f1 i1 e1 d1 c1 b1 a1 j0 h0 g0 f0 i0 e0 d0 c0 b0 a0
j3 h3 g3 f3 i3 e3 d3 c3 b3 a3 j2 h2 g2 f2 i2 e2 d2 c2 b2 a2 j1 h1 g1 f1 i1 e1 d1 c1 b1 a1 j0 h0 g0 f0 i0 e0 d0 c0 b0 a0
RX_DATA_WIDTH = 20
RX_DATA_WIDTH = 40
8B/10B
8B/10B
RXDATA
RXDATA
MSB
MSB LSB
LSB
Received
Last
Received
First
Received
Last
Received
First
UG482_c4_22_111011
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English