Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 195
UG482 (v1.9) December 19, 2016
RX Clock Correction
Using RX Clock Correction
The user must follow the steps described in this section to use the receiver’s clock correction feature.
Enabling Clock Correction
Each GTP transceiver includes a clock correction circuit that performs clock correction by
controlling the pointers of the RX elastic buffer. To use clock correction, RXBUF_EN is set to
TRUE to turn on the RX elastic buffer, and CLK_CORRECT_USE is set to TRUE to turn on the
clock correction circuit.
Clock correction is triggered when the RX elastic buffer latency is too high or too low, and the clock
correction circuit detects a match sequence. To use clock correction, the clock correction circuit
must be configured to set these items:
• RX elastic buffer limits
• Clock correction sequence
Setting RX Elastic Buffer Limits
The RX elastic buffer limits are set using CLK_COR_MIN_LAT (minimum latency) and
CLK_COR_MAX_LAT (maximum latency). When the number of bytes in the RX elastic buffer
drops below CLK_COR_MIN_LAT, the clock correction circuit writes an additional
CLK_COR_SEQ_LEN byte from the first clock correction sequence it matches to prevent buffer
underflow. Similarly, when the number of bytes in the RX elastic buffer exceeds
CLK_COR_MAX_LAT, the clock correction circuit deletes CLK_COR_SEQ_LEN bytes from the
first clock correction sequence it matches, starting with the first byte of the sequence. The 7 Series
FPGAs Transceivers Wizard chooses an optimal setting for CLK_COR_MIN_LAT and
CLK_COR_MAX_LAT based on application requirements. The values selected by the Wizard must
be followed to maintain optimal performance and must not be overridden.
RX_DISPERR_SEQ_MATCH String Specifies whether the disparity error status of a decoded byte must match the
indicator in the channel bonding and clock correction sequence.
TRUE: The disparity error status must be matched.
FALSE: The disparity error status is ignored.
ALIGN_COMMA_WORD Integer This attribute controls the alignment of detected commas within a multi-byte
datapath.
1: Align the comma to either of the 2 bytes for a 2-byte interface and any of
the 4 bytes for a 4-byte interface.
The comma can be aligned to either the even bytes or the odd bytes of the
RXDATA output.
2: Align the comma to the even bytes only. The aligned comma is guaranteed
to be aligned to even bytes RXDATA[9:0] for a 2-byte interface and
RXDATA[9:0]/RXDATA[29:20] for a 4-byte interface.
Refer to Figure 4-30 for comma alignment boundaries that are allowed for the
different ALIGN_COMMA_WORD and RX_DATA_WIDTH settings.
Protocols that send commas in even and odd positions must set
ALIGN_COMMA_WORD to 1.
Table 4-37: RX Clock Correction Attributes (Cont’d)
Attribute Type Description
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English