Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 157
UG482 (v1.9) December 19, 2016
RX Polarity Control
RX Polarity Control
Functional Description
If RXP and RXN differential traces are accidentally swapped on the PCB, the differential data
received by the GTP transceiver RX are reversed. The GTP transceiver RX allows inversion to be
done on parallel bytes in the PCS after the SIPO to offset reversed polarity on differential pair.
Polarity control function uses the RXPOLARITY input, which is driven High from the fabric user
interface to invert the polarity.
Ports and Attributes
Table 4-22 defines the ports required by the RX polarity control function.
RXOUT_DIV Integer PLL0 or PLL1 output clock divider D for the RX datapath as shown in Figure 2-9, page 35.
Valid settings are 1, 2, 4, or 8.
This attribute sets the divider only if the RXRATE port is set to 3'b000.
USE_PCS_CLK_PHASE
_SEL
1-bit
Binary
If set to 1, Eye Scan 4T clock phase is determined by ES_CLK_PHASE_SEL.
If set to 0, deserializer phase detector determines phase of Eye Scan 4T clock.
ES_CLK_PHASE_SEL 1-bit
Binary
If USE_PCS_CLK_PHASE_SEL is asserted, setting to 1 selects one phase of Eye Scan 4T clock.
Setting to 0 selects the other phase.
Table 4-20: RX Margin Analysis Attributes (Cont’d)
Attribute Type Description
Table 4-21: DRP Address Map for Eye Scan Read-Only (R) Registers
DRP Address
Hex
DRP Bits R/W Name Attribute Bit
151 15:0 R es_error_count 15:0
152 15:0 R es_sample_count 15:0
153 3:0 R es_control_status 3:0
154 15:0 R es_rdata 79:64
155 15:0 R es_rdata 63:48
156 15:0 R es_rdata 47:32
157 15:0 R es_rdata 31:16
158 15:0 R es_rdata 15:0
159 15:0 R es_sdata 79:64
15A 15:0 R es_sdata 63:48
15B 15:0 R es_sdata 47:32
15C 15:0 R es_sdata 31:16
15D 15:0 R es_sdata 15:0
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English