Xilinx 7 Series User Manual

206 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
one-half the minimum distance (in bytes or 10-bit codes) between channel bonding sequences. This
minimum distance is determined by the protocol being used.
Precedence between Channel Bonding and Clock Correction
The clock correction (see RX Clock Correction, page 191) and channel bonding circuits both
perform operations on the pointers of the RX elastic buffer. Normally, the two circuits work together
without conflict, except when clock correction events and channel bonding events occur
simultaneously. In this case, one of the two circuits must take precedence. To make clock correction
a higher priority than channel bonding, CLK_COR_PRECEDENCE must be set to TRUE. To make
channel bonding a higher priority, CLK_COR_PRECEDENCE must be set to FALSE.
RX Gearbox
Functional Description
The RX gearbox provides support for 64B/66B and 64B/67B header and payload separation. The
gearbox uses output ports RXDATA[31:0] and RXHEADER[2:0] for the payload and header of the
received data. Similar to TX Gearbox, page 86, the RX gearbox operates with the PMA using a
single clock. Because of this, occasionally, the output data is invalid. Output ports
RXHEADERVALID and RXDATAVALID determine if the appropriate header and data are valid.
The RX gearbox supports 2-byte and 4-byte interfaces.
The data out of the RX gearbox is not necessarily aligned. Alignment is done in the FPGA logic. The
RXGEARBOXSLIP port can be used to slip the data from the gearbox cycle-by-cycle until correct
alignment is reached. It takes a specific number of cycles before the bitslip operation is processed
and the output data is stable. Descrambling of the data and block synchronization is done in the
FPGA logic.
Ports and Attributes
Table 4-41 defines the RX gearbox ports.
Table 4-41: RX Gearbox Ports
Port Name Dir Clock Domain Description
RXDATAVALID[1:0] Out RXUSRCLK2 • Bit 0: Status output when Gearbox 64B/66B or 64B/67B is used, which
indicates that the data appearing on RXDATA is valid. For example,
during 64B/66B encoding, this signal is deasserted every 32 cycles for
the 4-byte interface and every 64 cycles for the 2-byte interface.
•Bit 1: Reserved.
RXGEARBOXSLIP In RXUSRCLK2 When High, this port causes the gearbox contents to slip to the next
possible alignment. This port is used to achieve alignment with the FPGA
logic. Asserting this port for one RXUSRCLK2 cycle changes the data
alignment coming out of the gearbox.
RXGEARBOXSLIP must be deasserted for at least one cycle and then
reasserted to cause a new realignment of the data. If multiple realignments
occur in rapid succession, it is possible to pass the proper alignment point
without recognizing the correct alignment point in the FPGA logic.
RXHEADER[2:0] Out RXUSRCLK2 Header outputs for 64B/66B (1:0) and 64B/67B (2:0).
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English