Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 207
UG482 (v1.9) December 19, 2016
RX Gearbox
Table 4-42 defines the RX gearbox attributes.
Enabling the RX Gearbox
To enable the RX gearbox for the GTP transceiver, set the attribute RXGEARBOX_EN to TRUE.
The GEARBOX_MODE attribute controls the GTP transceiver’s TX and RX gearbox use modes.
RX Gearbox Operating Modes
The RX gearbox supports 2-byte and 4-byte logic interfaces to the FPGA logic.
As shown in Figure 4-53, either mode uses the RXDATA, RXHEADER, RXDATAOUTVALID,
and RXHEADEROUTVALID outputs in addition to the RXGEARBOXSLIP input.
RXHEADERVALID Out RXUSRCLK2 Indicates that the RXHEADER is valid when using the gearbox.
RXSTARTOFSEQ Out RXUSRCLK2 When the gearbox 64B/66B or 64B/67B is enabled, this output indicates
when the sequence counter is 0 for the present RXDATA outputs.
Table 4-41: RX Gearbox Ports (Cont’d)
Port Name Dir Clock Domain Description
Table 4-42: RX Gearbox Attributes
Attribute Type Description
GEARBOX_MODE 3-bit Binary This attribute indicates the TX and RX gearbox modes:
• Bit 2: Set to 0. Unused.
• Bit 1: Set to 0.
0: Use the external sequence counter and apply inputs to TXSEQUENCE in the TX
gearbox.
• Bit 0:
0: 64B/67B gearbox mode for Interlaken
1: 64B/66B gearbox
RXGEARBOX_EN String When TRUE, this attribute enables the RX gearbox.
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English