Home
Xilinx
Computer Hardware
7 Series
Xilinx 7 Series User Manual
4
of 1
of 1 rating
306 pages
Give review
Manual
Specs
To Next Page
To Next Page
To Previous Page
To Previous Page
Loading...
7
Series FPGAs GTP T
ransceivers User Guide
www
.xil
inx.com
247
UG482 (v1.9) December 19, 2016
FBG676 Packag
e Placement Dia
gram
X-Ref Target - Figure A
-10
Figure A-10:
Placement Diagram for the FBG676 Package (2 of 2)
AE7
MGTPTXP3_213
AF7
MGTPTXN3_213
AE11
MGTPRXP3_213
AF11
MGTPRXN3_213
AC8
MGTPTXP2_2
13
UG482_aA_06_021113
AD8
MGTPTXN2_2
13
AC14
MGTPRXP2_213
AD14
MGTPRXN2_213
AA11
MGTREFCLK1P_213
AB11
MGTREFCLK1N_213
AA13
MGTREFCLK0P_213
AB13
MGTREFCLK0N_213
AE9
MGTPTXP1_213
AF9
MGTPTXN1_213
AE13
MGTPRXP1_213
AF13
MGTPRXN1_213
AC10
MGTPTXP0_213
AD10
MGTPTXN0_213
AC12
MGTPRXP0_213
AD12
MGTPRXN0_213
XC7A200T:
GTPE2_CHANNEL_X0Y3
XC7A200T:
GTPE2_CHANNEL_X0Y2
XC7A200T:
GTPE2_COMMON_X0Y0
XC7A200T:
GTPE2_CHANNEL_X0Y1
XC7A200T:
GTPE2_CHANNEL_X0Y0
S
e
n
d
F
e
e
d
b
a
c
k
246
248
Table of Contents
Default Chapter
2
Revision History
2
Table of Contents
5
Preface: about this Guide
9
Guide Contents
9
Additional Resources
10
Additional References
10
Chapter 1 : Transceiver and Tool Overview
11
Overview and Features
11
Series Fpgas Transceivers Wizard
16
Simulation
16
Implementation
20
Chapter 2: Shared Features
23
Reference Clock Input Structure
23
Reference Clock Selection and Distribution
25
Pll
34
Reset and Initialization
38
Power down
61
Loopback
64
Dynamic Reconfiguration Port
67
Digital Monitor
70
Chapter 3: Transmitter
75
TX Overview
75
FPGA TX Interface
76
TX 8B/10B Encoder
83
Running Disparity
84
TX Gearbox
86
TX Buffer
93
TX Buffer Bypass
95
TX Pattern Generator
103
TX Polarity Control
106
TX Fabric Clock Output Control
107
TX Phase Interpolator PPM Controller
111
TX Configurable Driver
114
TX Receiver Detect Support for PCI Express Designs
121
TX Out-Of-Band Signaling
123
Chapter 4 : Receiver
125
RX Overview
125
RX Analog Front End
126
RX Out-Of-Band Signaling
131
RX Equalizer
139
Rx Cdr
141
RX Fabric Clock Output Control
146
RX Margin Analysis
150
RX Polarity Control
157
RX Pattern Checker
158
RX Byte and Word Alignment
160
Enabling Comma Alignment
161
Configuring Comma Patterns
161
Activating Comma Alignment
162
Alignment Status Signals
162
Alignment Boundaries
163
Manual Alignment
164
RX 8B/10B Decoder
169
Rx Running Disparity
170
Special Characters
171
RX Buffer Bypass
173
RX Elastic Buffer
186
RX Clock Correction
190
Enabling Clock Correction
195
Setting Clock Correction Sequences
196
RX Channel Bonding
197
Enabling Channel Bonding
202
Channel Bonding Mode
202
Connecting Channel Bonding Ports
202
Setting the Maximum Skew
205
RX Gearbox
206
FPGA RX Interface
213
Chapter 5: Board Design Guidelines
217
Overview
217
Pin Description and Design Guidelines
217
Reference Clock
224
Gtp Reference Clock Checklist
226
Power Supply and Filtering
228
Selectio Usage Guidelines
235
PCB Design Checklist
235
Appendix A: Placement Information by Package
237
CPG236 Package Placement Diagram
238
CSG325 Package Placement Diagram
239
CLG485 Package Placement Diagram
240
FGG484 Package Placement Diagram
241
FGG676 Package Placement Diagram
242
FBG484 Package Placement Diagram
244
SBG484 Package Placement Diagram
245
FBG676 Package Placement Diagram
246
FFG1156 Package Placement Diagram
248
4
Based on 1 rating
Ask a question
Give review
Questions and Answers:
Need help?
Do you have a question about the Xilinx 7 Series and is the answer not in the manual?
Ask a question
Xilinx 7 Series Specifications
General
Brand
Xilinx
Model
7 Series
Category
Computer Hardware
Language
English
Related product manuals
Xilinx Spartan-7 SP701
4 pages
Xilinx Virtex-7 VC7203
77 pages
Xilinx Artix-7 FPGA AC701
40 pages
Xilinx Kintex-7 FPGA KC705
40 pages
Virtex-7 FPGA VC7222 IBERT
68 pages
Xilinx Alveo U250
26 pages
MIcroBlaze Development Spartan-3E 1600E Kit
168 pages
Xilinx MicroBlaze
18 pages
Xilinx Alveo U50
31 pages
Xilinx Alveo U200
53 pages
Xilinx ChipScope Pro
226 pages
To Next PageTo Next PageTo Previous PageTo Previous Page
Loading...
Need help?
General
