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inx.com
7
Series
FPGAs GTP T
ransceivers User Guid
e
UG482 (v1.9) December 19, 2016
Appendix A:
Placement
Information by
Package
X-Ref Target - Figure A
-13
Figure A
-13:
Placement Diagram for the FFG1
156 Package (3 of 4)
AN23
MGTPTXP3_213
AP23
MGTPTXN3_213
AJ21
MGTPRXP3_213
AK21
MGTPRXN3_213
AL22
MGTPTXP2_213
UG482_aA_09_021113
AM22
MGTPTXN2_213
AL20
MGTPRXP2_213
AM20
MGTPRXN2_213
AG18
MGTREFCLK1P_213
AH18
MGTREFCLK1N_213
AG20
MGTREFCLK0P_213
AH20
MGTREFCLK0N_213
AN21
MGTPTXP1_213
AP21
MGTPTXN1_213
AJ19
MGTPRXP1_213
AK19
MGTPRXN1_213
AN19
MGTPTXP0_213
AP19
MGTPTXN0_213
AL18
MGTPRXP0_213
AM18
MGTPRXN0_213
XC7A200T:
GTPE2_CHANNEL_X0Y3
XC7A200T:
GTPE2_CHANNEL_X0Y2
XC7A200T:
GTPE2_COMMON_X0Y0
XC7A200T:
GTPE2_CHANNEL_X0Y1
XC7A200T:
GTPE2_CHANNEL_X0Y0
S
e
n
d
F
e
e
d
b
a
c
k
249
251
Table of Contents
Default Chapter
2
Revision History
2
Table of Contents
5
Preface: about this Guide
9
Guide Contents
9
Additional Resources
10
Additional References
10
Chapter 1 : Transceiver and Tool Overview
11
Overview and Features
11
Series Fpgas Transceivers Wizard
16
Simulation
16
Implementation
20
Chapter 2: Shared Features
23
Reference Clock Input Structure
23
Reference Clock Selection and Distribution
25
Pll
34
Reset and Initialization
38
Power down
61
Loopback
64
Dynamic Reconfiguration Port
67
Digital Monitor
70
Chapter 3: Transmitter
75
TX Overview
75
FPGA TX Interface
76
TX 8B/10B Encoder
83
Running Disparity
84
TX Gearbox
86
TX Buffer
93
TX Buffer Bypass
95
TX Pattern Generator
103
TX Polarity Control
106
TX Fabric Clock Output Control
107
TX Phase Interpolator PPM Controller
111
TX Configurable Driver
114
TX Receiver Detect Support for PCI Express Designs
121
TX Out-Of-Band Signaling
123
Chapter 4 : Receiver
125
RX Overview
125
RX Analog Front End
126
RX Out-Of-Band Signaling
131
RX Equalizer
139
Rx Cdr
141
RX Fabric Clock Output Control
146
RX Margin Analysis
150
RX Polarity Control
157
RX Pattern Checker
158
RX Byte and Word Alignment
160
Enabling Comma Alignment
161
Configuring Comma Patterns
161
Activating Comma Alignment
162
Alignment Status Signals
162
Alignment Boundaries
163
Manual Alignment
164
RX 8B/10B Decoder
169
Rx Running Disparity
170
Special Characters
171
RX Buffer Bypass
173
RX Elastic Buffer
186
RX Clock Correction
190
Enabling Clock Correction
195
Setting Clock Correction Sequences
196
RX Channel Bonding
197
Enabling Channel Bonding
202
Channel Bonding Mode
202
Connecting Channel Bonding Ports
202
Setting the Maximum Skew
205
RX Gearbox
206
FPGA RX Interface
213
Chapter 5: Board Design Guidelines
217
Overview
217
Pin Description and Design Guidelines
217
Reference Clock
224
Gtp Reference Clock Checklist
226
Power Supply and Filtering
228
Selectio Usage Guidelines
235
PCB Design Checklist
235
Appendix A: Placement Information by Package
237
CPG236 Package Placement Diagram
238
CSG325 Package Placement Diagram
239
CLG485 Package Placement Diagram
240
FGG484 Package Placement Diagram
241
FGG676 Package Placement Diagram
242
FBG484 Package Placement Diagram
244
SBG484 Package Placement Diagram
245
FBG676 Package Placement Diagram
246
FFG1156 Package Placement Diagram
248
4
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Xilinx 7 Series Specifications
General
Brand
Xilinx
Model
7 Series
Category
Computer Hardware
Language
English
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