Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 101
UG074 (v2.2) February 22, 2010
Media Independent Interface (MII)
R
MII Clock Management
Figure 4-2 shows the clock management used with the MII interface. Both the
MII_TX_CLK_# and MII_RX_CLK_#, generated from the PHY, have a frequency of either
2.5 MHz or 25 MHz, depending on the operating speed of the Ethernet MACs. The
MII_TX_CLK drives the MII_TXD registers, the CLIENTEMAC#TXGMIIMIICLKIN and
the PHYEMAC#MIITXCLK through a BUFG. It has a frequency of 12.5 MHz or 1.25 MHz
depending on the operating speed of the Ethernet MAC. The RX clocking is similar.
The CLIENTEMAC#DCMLOCKED port must be tied High.
MII Clock Management with Clock Enable
It is possible to only use two BUFGs. To accomplish this BUFG reduction, the client and
MII logic must be constrained to run at 125 MHz. Also clock enable signals must be added
to the client logic. Figure 4-3 shows the MII clock management with a clock enable scheme.
Figure 4-2: MII Clock Management
CLIENTEMAC#TXGMIIMIICLKIN
PHYEMAC#GTXCLK
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
CLIENTEMAC#DCMLOCKED
PHYEMAC#RXCLK
EMAC#PHYTXD[3:0]
PHYEMAC#RXD[3:0]
EMAC#
BUFG
TX CLIENT
LOGIC
BUFG
RX CLIENT
LOGIC
IBUFG
MII_RX_CLK_#
DQ
MII_RXD_#[3:0]
IBUF
OBUF
MII_TXD_#[3:0]
Q D
BUFG
MII_TX_CLK_#
PHYEMAC#MIITXCLK
GND
UG074_3_51_032207
BUFG
(1)
Note 1: A regional buffer (BUFR) can replace this BUFG.
Refer to the Virtex-4 User Guide for BUFR usage guidelines.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English