Xilinx Virtex-4 User Manual

72 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
Host Interface
To access the Ethernet MAC registers through the host interface, the user must set
TIEEMACCONFIGURE[67] = 1. The host interface allows the user to:
• Program the configuration registers in the Ethernet MAC
• Read the accumulated statistics from the statistics unit implemented in the fabric
(optional)
• Access the configuration registers and multicast address table register in the address
filtering unit
• Access the Management Data I/O (MDIO) registers of the physical components
attached to the Ethernet MACs
The two Ethernet MACs share a single host interface. The host interface brings the Ethernet
MAC host bus from the Ethernet MAC out to the fabric. The host interface unit also
contains a DCR bus bridge. This allows the user to access the Ethernet MAC registers
through the DCR bus. Figure 3-38 shows the internal structure of the host interface. The
EMAC1 signal is provided by the HOSTEMAC1SEL input signal when using the generic
host bus or generated by the DCR bridge when using the DCR bus.
The DCREMACENABLE signal is used to select either the generic host bus or the DCR
bus. When this signal is asserted, the host interface uses the DCR bus.
Figure 3-38: Host Interface
DCR
Bridge
EMAC1
EMAC0
Host Interface
Generic Host Bus
DCR Bus
DCREMACENABLE
10
10
Ethernet MAC Block
Processor Block
Virtex- 4 FPGA
PPC405
DCRHOSTDONEIR
EMAC1
ug074_3_40_080805
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English